Active Pixel Sensor With Reduced Fixed Pattern Noise

• US 20100079643A1
• Filed: 03/27/2009
• Published: 04/01/2010
• Est. Priority Date: 04/23/1999
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Barna, Sandor L., Andersson, Anders
• Granted Patent: US 7,973,843 B2
• Time in Patent Office: Days
• US Class Current: 348/302
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14654 Blooming suppression
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

An image sensor includes pixels each of which is designed to transfer charge, accumulated in a photoactive region of the pixel during a first period, through a second active region of the pixel to a power supply node, and to transfer charge, accumulated in the photoactive region during a second period, through the second active region to a sense node in the pixel. Passing charge through the second active region prior to transferring it either to the power supply node or the sense node can help reduce fixed pattern noise. The image sensor can be operated in snap-shot mode.

Claims

1-24. -24. (canceled)

25. A pixel, comprising:

a first photoactive region in a substrate;

a second photoactive region in the substrate selectively connectable to the first photoactive region and operable to receive charge transferred from the first photoactive region;

a storage node selectively connectable to the second photoactive region; and

a power supply node selectively connectable to the storage node, wherein the pixel is operable to set an amount of charge in the second photoactive region at a predetermined level prior to a charge transfer from the first photoactive region.

26. The pixel of claim 25, wherein the first and second photoactive regions are separated by a first transfer gate.

27. The pixel of claim 25, wherein the storage node is a floating diffusion region.

28. The pixel of claim 25, wherein the storage node and second photoactive region are separated by a second transfer gate.

29. The pixel of claim 25, wherein the power supply node is an anti-blooming node.

30. The pixel of claim 25, wherein the pixel is operable to:

accumulate charge in the first photoactive region over a first integration period;

transfer the charge accumulated in the first photoactive region to the second photoactive region;

transfer the charge stored in the second photoactive region to the power supply node; and

reset the second photoactive region to the predetermined level.

31. The pixel of claim 30, wherein the pixel is operable to:

accumulate charge in the first photoactive region over a second integration period;

transfer the charge accumulated in the first photoactive region to the second photoactive region; and

transfer the charge stored in the second photoactive region to the storage node.

32. The pixel of claim 25, wherein the pixel is operable to:

read out a pixel signal level corresponding to charge previously transferred to the storage node;

reset the storage node;

reset the second photoactive region to the predetermined level;

transfer charge accumulated in the second active region to the storage node; and

read out a pixel signal level corresponding to charge transferred to the storage node.

33. A pixel, comprising:

first and second photosensitive elements separated by a first transfer gate; and

anti-blooming and storage regions selectively connectable to the second photosensitive element, the pixel being operable in any one of four modes;

a first mode in which charge is accumulated in the first photosensitive element;

a second mode in which charge is transferred from the first photosensitive element to the second photosensitive element;

a third mode in which charge is transferred from the second photosensitive element to the anti-blooming region; and

a fourth mode in which charge is transferred from the second photosensitive element to the storage region.

34. The pixel of claim 33, wherein the pixel is operable to be read out through the storage region.

35. The pixel of claim 33, wherein the anti-blooming region and second photosensitive element are separated by a second transfer gate.

36. The pixel of claim 35, wherein the storage region and second photosensitive element are separated by a third transfer gate.

37. The pixel of claim 33, wherein the pixel is further operable to receive control signals to cause the pixel to operate sequentially in the first, second, and third modes.

38. The pixel of claim 33, wherein the pixel is further operable to receive control signals to cause the pixel to operate sequentially in the first, second, and fourth modes.

39. The pixel of claim 33, wherein the pixel is further operable to cause a predetermined amount of charge to be transferred to the second photosensitive element prior to the pixel operating in the second mode.

40. A pixel array, comprising:

a plurality of pixels, each pixel including;

first and second photoactive regions separated by a first transfer gate,

anti-blooming and storage regions selectively connectable to the second photoactive region and separated from the second photoactive region by second and third transfer gates, respectively, and

a reset gate selectively connectable to the storage region; and

a controller operable to control the transfer and reset gates of the plurality of pixels.

41. The pixel array of claim 40, wherein the controller is operable to provide control signals to the transfer gates in each pixel to cause a predetermined amount of charge to be transferred to a respective second photoactive region prior to a charge transfer from a respective first photoactive region to a respective second photoactive region.

42. The pixel array of claim 40, wherein the controller is operable to provide control signals to each pixel to cause the pixels to transfer charge accumulated in their first photoactive regions during a common integration period to their respective storage nodes at substantially the same time.

43. The pixel array of claim 40, wherein the controller is operable to control the transfer and reset gates of each of the plurality of pixels in any one of four modes:

a first mode in which charge is accumulated in each first photoactive region;

a second mode in which charge is transferred from the first photoactive region through the first transfer gate to the second photoactive region;

a third mode in which charge is transferred from the second photoactive region through the second transfer gate to the anti-blooming region; and

a fourth mode in which charge is transferred from the second photoactive region through the third transfer gate to the storage region.

44. The pixel array of claim 40, wherein the controller is operable to:

set the second photoactive region of a pixel to a predetermined charge level;

cause charge accumulated in the first photoactive region of the pixel during a non-charge integration period to be transferred to the second active region of the pixel;

cause charge from the second active region to be transferred to the anti-blooming region of the pixel;

reset the second photoactive region to the predetermined charge level;

cause charge accumulated in the first photoactive region during a charge integration period to be transferred to the second active region of the pixel; and

cause charge from the second active region to be transferred to the storage region of the pixel.