Low resistivity single crystal silicon carbide wafer

• US 20100080956A1
• Filed: 12/01/2009
• Published: 04/01/2010
• Est. Priority Date: 05/23/2007
• Status: Active Grant

• Current Assignee: Resonac Corp. (Resonac Holdings Corp.)
• Original Assignee: Showa Denko KK
• Inventors: Katsuno, Masakazu, Nakabayashi, Masashi, Fujimoto, Tatsuo, Ohtani, Noboru, Yashiro, Hirokatsu
• Granted Patent: US 9,915,011 B2
• Time in Patent Office: Days
• US Class Current: 428/141
• CPC Class Codes: C30B 23/00 Single-crystal growth by condensing evaporated or sublimed materials
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/36 Carbides
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 33/02 Heat treatment C30B33/04, C30B33/06 take precedence
• CPC Class Codes: Y10T 428/24355 Continuous and nonuniform or irregular surface on layer or component [e.g., roofing, etc.]

Abstract

The invention provides a low resistivity silicon carbide single crystal wafer for fabricating semiconductor devices having excellent characteristics. The low resistivity silicon carbide single crystal wafer has a specific volume resistance of 0.001 Ωcm to 0.012 Ωcm and 90% or greater of the entire wafer surface area is covered by an SiC single crystal surface of a roughness (Ra) of 1.0 nm or less.

Claims

1. A low resistivity silicon carbide single crystal wafer having a specific volume resistance of 0.001 Ω

cm to 0.012 Ω

cm, 90% or greater of the entire wafer surface area of which is covered by an SiC single crystal surface of a roughness (Ra) of 1.0 nm or less.

2. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein 95% or greater of the entire surface area of the SiC single crystal wafer is covered by an SiC single crystal surface of a roughness (Ra) of 1.0 nm or less.

3. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the specific volume resistance is 0.001 Ω

cm to 0.009 Ω

cm.

4. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the surface roughness (Ra) is 0.6 nm or less.

5. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the surface roughness (Ra) is 0.3 nm or less.

6. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the crystal polytype of the SiC single crystal wafer is 4H.

7. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the thickness of the SiC single crystal wafer is 0.05 mm to 0.4 mm.

8. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the thickness of the SiC single crystal wafer is 0.05 mm to 0.25 mm.

9. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the offset angle of the SiC single crystal wafer from the {0001} face is 1°

to 12°

.

10. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the diameter of the wafer is 50 mm to 300 mm.

11. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the basal plane stacking fault density in the wafer after high-temperature annealing in the case of high-temperature annealing at 1000°

C. to 1800°

C. is 30 cm<sup>−

1</sup> or less.

12. A low resistivity silicon carbide single crystal wafer according to claim 1, wherein the basal plane stacking fault density in the wafer after high-temperature annealing in the case of high-temperature annealing at 1000°

C. to 1800°

C. is 10 cm<sup>−

1</sup> or less.

13. An SiC epitaxial wafer comprising an SiC film epitaxially grown on a low resistivity silicon carbide single crystal wafer according to claim 1.

14. An epitaxial wafer comprising a film of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN) or a mixed crystal thereof epitaxially grown on a low resistivity silicon carbide single crystal wafer according to claim 1.