Sequencing Decoder Circuit

• US 20100085830A1
• Filed: 10/07/2009
• Published: 04/08/2010
• Est. Priority Date: 10/07/2008
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel R.
• Granted Patent: US 8,325,556 B2
• Time in Patent Office: Days
• US Class Current: 365/230.60
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

Claims

1. A memory-array decoder receiving as input a plurality of address bits and operably coupled to a memory array comprising a sequence of rows, the decoder comprising:

a first decoder stage for selecting one or more first rows by decoding a first subset of the address bits; and

a second decoder stage for selecting one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

2. The decoder of claim 1, wherein the one or more second rows are selected by incrementing the locations of the one or more third rows.

3. The decoder of claim 1, wherein the one or more third rows are selected by an applied signal different from the plurality of address bits.

4. The decoder of claim 1, wherein the one or more third rows are selected by an applied signal different from the plurality of address bits in conjunction with a second subset of the address bits.

5. The decoder of claim 4, wherein the first subset of the address bits and the second subset of the address bits are different.

6. The decoder of claim 5, wherein no address bits in the first subset are within the second subset.

7. The decoder of claim 1, wherein the second stage is capable of selecting the one or more second rows from all rows in the memory array.

8. The decoder of claim 1, wherein the plurality of address bits comprises an input memory address and its complement.

9. The decoder of claim 1, wherein the first stage selects a single first row from the one or more second rows selected by the second stage.

10. The decoder of claim 1, wherein the memory array is programmed with data comprising at least one of music, video, computer software, a computer application, reference data, text, or a diagram.

11. The decoder of claim 1, wherein the decoder and memory array are disposed within a removable memory storage device.

12. The decoder of claim 1, wherein the memory array comprises a plurality of storage cells, at least one of which comprises a phase-change material.

13. A method of forming a memory-array decoder receiving as input a plurality of address bits and operably coupled to a memory array comprising a sequence of rows, the method comprising:

providing a first decoder stage for selecting one or more first rows by decoding a first subset of the address bits; and

providing a second decoder stage for selecting one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

14. A method of decoding a memory array comprising a sequence of rows, the method comprising:

receiving as input, by a decoder, a plurality of address bits;

selecting, with a first stage of the decoder, one or more first rows by decoding a first subset of the address bits; and

selecting, with a second stage of the decoder, one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

15. The method of claim 14, wherein the one or more second rows are selected by incrementing the locations of the one or more third rows.

16. The method of claim 14, further comprising applying a signal different from the plurality of address bits to the decoder to select the one or more third rows.

17. The method of claim 14, further comprising, to select the one or more third rows, applying a signal different from the plurality of address bits to the decoder and decoding a second subset of the address bits.

18. The method of claim 17, wherein the first subset of the address bits and the second subset of the address bits are different.

19. The method of claim 18, wherein no address bits in the first subset are within the second subset.

20. The method of claim 14, wherein the second stage is capable of selecting the one or more second rows from all rows in the memory array.

21. The method of claim 14, wherein the plurality of address bits comprises an input memory address and its complement.

22. The method of claim 14, wherein selecting the one or more first rows comprises selecting, with the first stage, a single row from the one or more second rows selected by the second stage.