Transistor, semiconductor device including a transistor and methods of manufacturing the same

• US 20100102397A1
• Filed: 04/17/2009
• Published: 04/29/2010
• Est. Priority Date: 10/27/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Kiha, Song, Ihun, Park, Sungho
• Granted Patent: US 8,035,101 B2
• Time in Patent Office: Days
• US Class Current: 257/392
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor, a semiconductor device including the transistor and methods of manufacturing the same are provided, the transistor including a threshold voltage adjusting layer contacting a channel layer. A source electrode and a drain electrode contacting may be formed opposing ends of the channel layer. A gate electrode separated from the channel layer may be formed. A gate insulating layer may be formed between the channel layer and the gate electrode.

Claims

1. A transistor, comprising:

a first channel layer;

a first threshold voltage adjusting layer contacting the first channel layer;

a first source electrode and a first drain electrode contacting opposing ends of the first channel layer;

a first gate electrode separated from the first channel layer; and

a first gate insulating layer between the first channel layer and the first gate electrode,

wherein the first channel layer is between the first threshold voltage adjusting layer and the first gate insulating layer.

2. The transistor of claim 1, wherein the first threshold voltage adjusting layer has a work function that is different from a work function of the first channel layer.

3. The transistor of claim 1, wherein the first threshold voltage adjusting layer is separated from the first source electrode and the first drain electrode.

4. The transistor of claim 1, wherein the first threshold voltage adjusting layer includes at least one selected from group consisting of a metal and a semiconductor.

5. The transistor of claim 4, wherein the semiconductor is doped with conductive impurities.

6. The transistor of claim 1, wherein the first channel layer is an oxide layer.

7. The transistor of claim 1, wherein the first gate electrode is above the first channel layer.

8. The transistor of claim 1, wherein the first gate electrode is below the first channel layer.

9. The transistor of claim 7, further comprising:

an insulating layer on the first threshold voltage adjusting layer, the insulating layer having a hole that exposes a portion of the first threshold voltage adjusting layer,

wherein the first channel layer contacts the exposed portion of the first threshold voltage adjusting layer.

10. The transistor of claim 7, wherein the first threshold voltage adjusting layer is on a substrate, and the first channel layer covers a top surface and side surfaces of the first threshold voltage adjusting layer.

11. The transistor of claim 7, further comprising:

an insulating layer having a groove on a substrate,

wherein the first threshold voltage adjusting layer is in the groove, and the first channel layer is on the insulating layer such that the first channel layer covers the first threshold voltage adjusting layer.

12. A semiconductor device, comprising:

a first transistor and a second transistor,

wherein the first transistor is the transistor according to claim 1.

13. The semiconductor device of claim 12, wherein the first transistor and the second transistor have threshold voltages that are different from each other.

14. The semiconductor device of claim 13, wherein one of the first and second transistors is an enhancement mode transistor and the other of the first and second transistors is a depletion mode transistor.

15. The semiconductor device of claim 12, wherein the second transistor includes:

a second channel layer;

a second threshold voltage adjusting layer contacting the second channel layer;

a second source electrode and a second drain electrode contacting opposing ends of the second channel layer;

a second gate electrode separated from the second channel layer; and

a second gate insulating layer between the second channel layer and the second gate electrode,

wherein the second channel layer is between the second threshold voltage adjusting layer and the second gate insulating layer.

16. The semiconductor device of claim 15, wherein the second threshold voltage adjusting layer has a work function that is different from a work function of the second channel layer.

17. The semiconductor device of claim 15, wherein the first threshold voltage adjusting layer has a work function larger than a work function of the first channel layer, and the second threshold voltage adjusting layer has a work function smaller than a work function of the second channel layer.

18. The semiconductor device of claim 15, wherein the first threshold voltage adjusting layer has a work function smaller than a work function of the first channel layer, and the second threshold voltage adjusting layer has a work function larger than a work function of the second channel layer.

19. The semiconductor device of claim 15, wherein the second threshold voltage adjusting layer is separated from the second source electrode and the second drain electrode.

20. The semiconductor device of claim 15, wherein the second threshold voltage adjusting layer includes at least one selected from the group consisting of a metal and a semiconductor.

21. The semiconductor device of claim 20, wherein the semiconductor is doped with conductive impurities.

22. The semiconductor device of claim 15, wherein the first and second channel layers are formed of a same material.

23. The semiconductor device of claim 12, wherein the semiconductor device is a logic device.