Capacitance Measurement Circuit and Capacitance Measurement Method Thereof

• US 20100102831A1
• Filed: 09/30/2009
• Published: 04/29/2010
• Est. Priority Date: 10/29/2008
• Status: Active Grant

• Current Assignee: Raydium Semiconductor Corporation
• Original Assignee: Raydium Semiconductor Corporation
• Inventors: Kuang, Yu
• Granted Patent: US 8,289,034 B2
• Time in Patent Office: Days
• US Class Current: 324/676
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24

Abstract

A capacitance measurement circuit and a capacitance measurement method thereof. The capacitance measurement circuit for measuring a capacitor under test includes a capacitance to time unit, a continuous time integrator and an analog to digital converter. The capacitance to time unit generates a first clock signal and a second clock signal reverse to the first clock signal according to a first charge time of the capacitor under test and a second charge time of a variable capacitor. The continuous time integrator receives the first clock signal and outputs an integral signal according to the first clock signal. When the number of clocks of the second clock signal is equal to a default value, the analog to digital converter outputs a digital signal corresponding to a capacitance difference between the capacitor under test and the variable capacitor according to the integral signal.

Claims

1. A capacitance measurement circuit for measuring a capacitor under test, the capacitance measurement circuit comprising:

a capacitance to time unit for generating a first clock signal and a second clock signal reverse to the first clock signal according to a first charge time of the capacitor under test and a second charge time of a variable capacitor;

a continuous time integrator for receiving the first clock signal and outputting an integral signal according to the first clock signal; and

an analog to digital converter for outputting a digital signal corresponding to a capacitance difference between the capacitor under test and the variable capacitor according to the integral signal when the number of clocks of the second clock signal is equal to a default value.

2. The circuit according to claim 1, further comprising:

a counter for outputting a first enable signal when the number of clocks of the second clock signal is equal to the default value; and

a control logic for outputting a second enable signal according to the first enable signal to control the analog to digital converter to output the digital signal according to the integral signal.

3. The circuit according to claim 2, wherein:

the control logic further enables a first control signal in a voltage setting period to drive the continuous time integrator to set the integral signal to be equal to an initial voltage, and disables a second control signal reverse to the first control signal, and further enables the second control signal after the voltage setting period to connect the capacitance to time unit to the continuous time integrator so that the first clock signal charges/discharges the continuous time integrator; and

the counter further resets in response to an enabled level of the first control signal to recount the number of clocks of the second clock signal.

4. The circuit according to claim 2, wherein:

the capacitance to time unit further comprises a variable capacitor circuit for providing the variable capacitor;

the control logic further determines a signal value of a setting signal in a capacitance setting period so that the variable capacitor circuit adjusts an equivalent capacitance of the variable capacitor according to the signal value; and

the control logic further disables a third control signal in the capacitance setting period.

5. The circuit according to claim 4, wherein the capacitance to time unit further comprises:

a current source for providing a first current;

a switch circuit for selectively providing the first current to the capacitor under test or the variable capacitor according to inversion signals of the first clock signal and the second clock signal; and

a logic unit for generating the first clock signal and the second clock signal according to a reference voltage, a first charge voltage of the capacitor under test and a second charge voltage of the variable capacitor.

6. The circuit according to claim 5, wherein:

when the second charge voltage is higher than the reference voltage, the first clock signal is converted from a high voltage level into a low voltage level; and

when the first charge voltage is greater than the reference voltage, the second clock signal is converted from the high voltage level into the low voltage level.

7. The circuit according to claim 1, wherein the continuous time integrator comprises:

a first resistor;

a first switch selectively electrically connected to the first resistor and the capacitance to time unit, wherein the first switch is turned on in response to an enabled level of a second control signal to electrically connect the first resistor to the capacitance to time unit;

an operational amplifier, which comprises;

an inverting input terminal, connected to the first resistor, for receiving the first clock signal;

a noninverting input terminal for receiving an initial voltage; and

an output terminal connected to an input terminal of the analog to digital converter;

a first capacitor, wherein the inverting input terminal is coupled to the output terminal through the first capacitor;

a second switch selectively electrically connected to the inverting input terminal and the output terminal, wherein the second switch is turned on in response to an enabled level of a first control signal to electrically connect the inverting input terminal to the output terminal, and to set voltages of the inverting input terminal and the output terminal to be equal to the initial voltage.

8. The circuit according to claim 7, wherein the continuous time integrator circuit further comprises a second capacitor and a third switch, which are serially connected to the inverting input terminal and the output terminal, wherein the third switch is turned on in response to an enabled level of a third control signal so that the first capacitor is connected to the second capacitor in parallel.

9. A capacitance measurement method for measuring a capacitor under test, the capacitance measurement method comprising the steps of:

(a) setting an integral signal, outputted from a continuous time integrator, to be equal to an initial voltage;

(b) generating a first clock signal and a second clock signal reverse to each other according to a first charge time of the capacitor under test and a second charge time of a variable capacitor;

(c) outputting the first clock signal to the continuous time integrator and outputting the integral signal according to the first clock signal; and

(d) outputting a digital signal corresponding to a capacitance difference between the capacitor under test and the variable capacitor according to the integral signal when the number of clocks of the second clock signal is equal to a default value.

10. The method according to claim 9, wherein the step (d) comprises:

(d1) outputting a first enable signal when the number of clocks of the first clock signal is equal to a default value; and

(d2) outputting a second enable signal according to the first enable signal to control an analog to digital converter to output the digital signal according to the integral signal.

11. The method according to claim 9, wherein the step (b) comprises:

(b1) providing a first current;

(b2) providing the variable capacitor according to a capacitance setting signal;

(b3) selectively providing the first current to the capacitor under test or the variable capacitor according to inversion signals of the first clock signal and the second clock signal; and

(b4) generating the first clock signal and the second clock signal according to a reference voltage, a first charge voltage of the capacitor under test and a second charge voltage of the variable capacitor.

12. The method according to claim 11, wherein in the step (b4), the first clock signal is converted from a high voltage level into a low voltage level when the second charge voltage is higher than the reference voltage, and the second clock signal is converted from the high voltage level into the low voltage level when the first charge voltage is higher than the reference voltage.

13. The method according to claim 9, further comprising the step of:

(e) adjusting a capacitance of the variable capacitor to approximate a capacitance of the capacitor under test according to a capacitance setting signal.

14. The method according to claim 9, further comprising, before the step (a), the steps of:

(f) providing a setting signal to set a variable capacitor circuit so that the variable capacitor circuit adjusts an equivalent capacitance of the variable capacitor according to the setting signal;

(g) setting the integral signal, outputted from the continuous time integrator, to be equal to the initial voltage;

(h) outputting the first clock signal to the continuous time integrator, and outputting the integral signal according to the first clock signal;

(i) outputting a first enable signal to enable an analog to digital converter to sample the integral signal when the number of clocks of the second clock signal is equal to a default value;

(j) outputting a second enable signal according to the first enable signal to control the analog to digital converter to output a digital signal corresponding to a capacitance difference between the capacitor under test and the variable capacitor according to the sampled integral signal;

(k) judging whether or not the digital signal satisfies a critical condition and approximates to a reference digital signal, and performing step (l) if not, or performing step (m) if yes;

(l) adjusting a value of the setting signal and repeating the step (g); and

(m) determining the equivalent capacitance according to the value of the setting signal.

15. The method according to claim 14, further comprising, between the steps (g) and (h), the step of:

(n) reducing an equivalent capacitance of a feedback integrator capacitor of the continuous time integrator in response to a control signal.