Self Auto-Calibration of Analog Circuits in a Mixed Signal Integrated Circuit Device

• US 20100103005A1
• Filed: 09/15/2009
• Published: 04/29/2010
• Est. Priority Date: 10/27/2008
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Blake, Komen, Nolan, James B.
• Granted Patent: US 7,973,684 B2
• Time in Patent Office: Days
• US Class Current: 341/120
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45048 Calibrating and standardising a dif amp
• CPC Class Codes: H03F 2203/45136 One differential amplifier in IC-block form being shown
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold
• CPC Class Codes: H03M 1/1009 Calibration
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

Auto-calibration of the analog circuits occurs when requested by a user and/or the occurrence of an event(s). The user may invoke an auto-calibration on demand through an auto-calibration (A_CAL) input to the mixed-signal integrated circuit. An external voltage calibration (V_CAL) input may be used for auto-calibration of the mixed-signal integrated circuit to a user-supplied common-mode voltage reference. Auto-calibration of the mixed-signal integrated circuit may also be initiated upon the occurrence of any one or more of the following events: 1) detection of auto-calibration data corruption, e.g., parity checking of auto-calibration data values digitally stored in the mixed-signal integrated circuit; 2) an internal timer that causes a calibration request after a programmable timeout period, 3) change in the internal integrated circuit die temperature as determined by a temperature sensor, and 4) a change in the power supply and/or internal supply voltage(s).

Claims

1. An integrated circuit having at least one analog input device and an auto-calibration circuit to minimize input offset voltage in at least one analog input device, comprising:

at least one analog input device having a digitally controlled input offset voltage compensation circuit; and

an auto-calibration circuit, said auto-calibration circuit being coupled to said at least one analog input device and to the input offset voltage compensation circuit, wherein input offset voltage is minimized in said at least one analog input device during an auto-calibration cycle that is initiated by an event.

2. The integrated circuit of claim 1, wherein the event is a user auto-calibration request.

3. The integrated circuit of claim 1, wherein the event is a power-on-reset.

4. The integrated circuit of claim 1, wherein the event is detection of a parity error in a stored auto-calibration data value.

5. The integrated circuit of claim 1, wherein the event is an ending time of an auto-calibration timer.

6. The integrated circuit of claim 5, wherein the auto-calibration timer time is programmable.

7. The integrated circuit of claim 1, wherein the event is a change in temperature of the integrated circuit.

8. The integrated circuit of claim 1, wherein the event is a change in supply voltage.

9. The integrated circuit of claim 1, wherein said at least one analog input device is a comparator.

10. The integrated circuit of claim 1, wherein said at least one analog input device is an operational amplifier having differential inputs and an output.

11. The integrated circuit of claim 10, wherein said auto-calibration circuit comprises:

a voltage comparator;

a voltage reference coupled to an input of the voltage comparator;

a voltage offset trim digital-to-analog converter (DAC);

voltage offset calibration switches;

a successive approximation register (SAR) having an input coupled to an output of the voltage comparator and outputs coupled to the voltage offset trim DAC; and

calibration logic, wherein when the event occurs the calibration logic controls the voltage offset calibration switches to

couple the differential inputs of the operational amplifier to the voltage reference, and

the output of the operational amplifier to another input of the voltage comparator;

whereby the voltage comparator causes the SAR to change an output value to the voltage offset trim DAC so as to minimize the input offset voltage of the at least one analog input device.

12. The integrated circuit of claim 11, further comprising an offset compensation latch register connected between the SAR and the voltage offset trim DAC, wherein the offset compensation latch register stores the SAR output value used to minimize the input offset voltage of the at least one analog input device.

13. The integrated circuit of claim 11, wherein the voltage reference is programmable.

14. The integrated circuit of claim 1, wherein said at least one analog input device is an operational amplifier having differential inputs, a first output and a calibration output.

15. The integrated circuit of claim 14, wherein said auto-calibration circuit comprises:

a voltage comparator;

a voltage reference coupled to an input of the voltage comparator;

a voltage offset trim digital-to-analog converter (DAC);

voltage offset calibration switches;

a successive approximation register (SAR) having an input coupled to an output of the voltage comparator and outputs coupled to the voltage offset trim DAC; and

calibration logic, wherein when the event occurs the calibration logic controls the voltage offset calibration switches to

couple the differential inputs of the operational amplifier to the voltage reference, and

the calibration output of the operational amplifier to another input of the voltage comparator;

whereby the voltage comparator causes the SAR to change an output value to the voltage offset trim DAC so as to minimize the input offset voltage of the at least one analog input device.

16. The integrated circuit of claim 15, wherein the first output of the operational amplifier is a tri-state output and is decoupled from the calibration output when the input offset voltage of the at least one analog input device is being minimized.

17. The integrated circuit of claim 15, further comprising an offset compensation latch register connected between the SAR and the voltage offset trim DAC, wherein the offset compensation latch register stores the SAR output value used to minimize the input offset voltage of the at least one analog input device.

18. The integrated circuit of claim 15, wherein the voltage reference is programmable.

19. The integrated circuit of claim 1, wherein said auto-calibration circuit causes said at least one analog input device to have high gain during the auto-calibration cycle.

20. The integrated circuit of claim 1, further comprising switches for selecting from a plurality of analog input devices each one thereof during respective auto-calibration cycles therefore.

21. The integrated circuit of claim 20, further comprising:

a plurality of voltage offset trim DACs; and

a plurality of offset compensation latch registers connected between the SAR and respective ones of the plurality of voltage offset trim DACs, wherein each one of the plurality of offset compensation latch registers stores the SAR output value used to minimize the input offset voltage of respective ones of the plurality of analog input devices.

22. A method for minimizing an input offset voltage in an analog input device upon an occurrence of an event, said method comprising the steps of:

(a) detecting an occurrence of an event;

(b) switching from a normal mode to an auto-calibration mode upon detection of the occurrence of the event an analog input device having an input offset voltage compensation circuit;

(c) applying a reference voltage to the analog input device;

(d) minimizing an input offset voltage of the analog input device by;

(i) measuring an output voltage of the analog input device; and

(ii) applying input offset compensation values to the input offset voltage compensation circuit until the output voltage from the analog input device is at a desired value and then storing the input offset compensation value that minimizes the input offset voltage of the analog input device; and

(e) switching the analog input device from the calibration mode to the normal mode.

23. The method of claim 22, wherein the event is a user auto-calibration request.

24. The method of claim 22, wherein the event is a power-on-reset.

25. The method of claim 22, wherein the event is detection of a parity error in a stored auto-calibration data value.

26. The method of claim 22, wherein the event is an ending time of an auto-calibration timer.

27. The method of claim 22, wherein the step of switching the analog input device to a calibration mode includes the step of configuring the analog input device for high gain.

28. The method of claim 22, wherein the step of applying a reference voltage further comprises the step of applying a programmable reference voltage.

29. The method of claim 22, wherein the analog input device is a plurality of analog input devices and steps (b)-(e) are repeated for each one of the plurality of analog input devices.