Integrated image processor

• US 20100104175A1
• Filed: 12/21/2009
• Published: 04/29/2010
• Est. Priority Date: 11/03/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Tyzx, Inc. (Intel Corporation)
• Inventors: Woodfill, John Iselin, Gordon, Gaile Gibson, Buck, Ronald John, Brown, Terrence Lee, Jurasek, David Walter
• Granted Patent: US 8,724,885 B2
• Time in Patent Office: Days
• US Class Current: 382/154
• CPC Class Codes: G06T 7/593 from stereo images
• CPC Class Codes: G06V 10/94 Hardware or software architectures specially adapted for image or video understanding
• CPC Class Codes: G06V 10/955 using specific electronic processors
• CPC Class Codes: G06V 20/56 exterior to a vehicle by using sensors mounted on the vehicle

Abstract

A system is disclosed. An input interface is configured to receive pixel data from two or more images. A pixel handling processor disposed on the substrate is configured to convert the pixel data into depth and intensity pixel data. In some embodiments, a foreground detector processor disposed on the substrate is configured to classify pixels as background or not background. In some embodiments, a projection generator disposed on the substrate is configured to generate a projection in space of the depth and intensity pixel data.

Claims

1. An system for image processor comprising:

an input interface configured to receive pixel data from two or more images; and

a pixel handling processor disposed on the substrate configured to convert the pixel data into depth and intensity pixel data; and

a foreground detector processor disposed on the substrate classifies pixels as background or not background.

2. A system as in claim 1, wherein the pixel handling processor and the projection generator process pixel data in parallel.

3. A system as in claim 1, further including a segmentation processor.

4. A system as in claim 1, further including an application processor.

5. A system as in claim 1, further including a projection generator disposed on the substrate configured to generate a projection in space of the depth and intensity pixel data.

6. A system as in claim 1, wherein the pixel handling processor includes an image grabbing processor.

7. A system as in claim 1, wherein the pixel handling processor includes a rectify processor.

8. A system as in claim 1, wherein the pixel handling processor includes a depth processor.

9. A system as in claim 1, wherein depth comprises disparity.

10. A system for image processor comprising:

an input interface configured to receive pixel data from two or more images;

a pixel handling processor disposed on the substrate configured to convert the pixel data into depth and intensity pixel data; and

a projection generator disposed on the substrate configured to generate a projection in space of the depth and intensity pixel data.

11. A system as in claim 10, wherein the pixel handling processor and the foreground detector processor process pixel data in parallel.

12. A system as in claim 10, further including a segmentation processor.

13. A system as in claim 10, further including an application processor.

14. A system as in claim 10, wherein the pixel handling processor includes an image grabbing processor.

15. A system as in claim 10 wherein the pixel handling processor includes a rectify processor.

16. A system as in claim 10, wherein the pixel handling processor includes a depth processor.

17. A system as in claim 10, wherein depth comprises disparity.