Method of Manufacturing a Trench Transistor Having a Heavy Body Region

• US 20100112767A1
• Filed: 01/11/2010
• Published: 05/06/2010
• Est. Priority Date: 11/14/1997
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sapp, Steven, Mo, Brian Sze-Ki, Chau, Duc, Probst, Dean Edward, Bencuya, Izak
• Granted Patent: US 8,476,133 B2
• Time in Patent Office: Days
• US Class Current: 438/237
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Claims

1-45. -45. (canceled)

46. A method of manufacturing a trench transistor comprising:

forming a plurality of trenches defined by a corresponding plurality of semiconductor mesas, a height of the plurality of mesas defining a depth of the plurality of trenches, the mesas having dopants of the first conductivity type;

lining each of the plurality of trenches with a thin layer of gate dielectric material;

substantially filling each dielectric-lined trench with conductive material to form a gate electrode of the transistor;

forming a doped well in the plurality of mesas to a depth that is less than the depth of the plurality of trenches, the doped well having dopants of a second conductivity type opposite to said first conductivity type;

forming a source region inside the doped well and extending to a depth that is less than the depth of the well, the source region having dopants of the first conductivity type; and

forming a heavy body structure inside the doped well, the heavy body structure including a region having dopants of the second conductivity type with a peak concentration occurring at a peak concentration depth below the depth of the source region and above the depth of the doped well.

47. The method of claim 46 further comprising forming a deep doped region having dopants of the second conductivity type, the deep doped region extending deeper than the depth of the trench.

48. The method of claim 47 wherein the step of forming a deep doped region forms a PN junction diode with the substrate that helps improve a breakdown voltage of the transistor.

49. The method of claim 47 wherein the deep doped region forms a termination structure.

50. The method of claim 46 wherein the step of substantially filling each dielectric-lined trench leaves a recess at an upper portion of each trench.

51. The method of claim 46 wherein the step of forming the heavy body structure comprises a double implant process.

52. The method of claim 51 wherein the double implant process comprises:

a first implant of dopants of the first conductivity type, at a first energy level and a first dosage to form a first doped portion of the heavy body structure; and

a second implant of dopants of the first conductivity type, at a second energy level and a second dosage to form a second doped portion of the heavy body structure.

53. The method of claim 52 wherein the first implant occurs at approximately the peak concentration depth.

54. The method of claim 52 wherein the first energy level is higher than the second energy level.

55. The method of claim 54 wherein the first dosage is higher than the second dosage.

56. The method of claim 46 wherein the step of forming the heavy body structure comprises a process of diffusing dopants of the second conductivity type.

57. The method of claim 46 wherein the step of forming the heavy body structure comprises implanting dopants of the second conductivity type at about the peak concentration depth.

58. The method of claim 46 wherein the step of forming a plurality of trenches comprises patterning and etching the plurality of trenches that extend in parallel along a longitudinal axis.

59. The method of claim 58 further comprising forming a contact area on the surface of the plurality of mesas.

60. The method of claim 59 wherein the step of forming the contact area comprises forming alternating source contact regions and heavy body contact regions.

64. The method of claim 46 wherein the source region is formed prior to the heavy body structure.

65. The method of claim 46 further comprising forming a drain contact region at a surface opposite to top surface of the plurality of mesas.

66. The method of claim 46 wherein the step of forming a heavy body structure forms an abrupt junction between the region having dopants of the second conductivity type and the well.

61-63. -63. (canceled)

67-73. -73. (canceled)