DIGITAL I/O SIGNAL SCHEDULER

• US 20100114376A1
• Filed: 11/04/2008
• Published: 05/06/2010
• Est. Priority Date: 11/04/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Inventors: Brodt, Jeremy W., Guido, Samuel J., Sieber, Jeffrey T.
• Granted Patent: US 8,140,723 B2
• Time in Patent Office: Days
• US Class Current: 700/275
• CPC Class Codes: F02D 41/20 Output circuits, e.g. for controlling currents in command coils
• CPC Class Codes: F02D 41/26 using computer, e.g. microprocessor
• CPC Class Codes: F02D 41/263 the program execution being modifiable by physical parameters
• CPC Class Codes: F02P 5/15 Digital data processing
• CPC Class Codes: Y02T 10/40 Engine management systems

Abstract

An apparatus and method of scheduling signals. In one embodiment, the method includes a first circuit receiving a first plurality of reference values. The first circuit selects a reference value from the first plurality according to a first reference identifier (ID) that is stored in memory. The first circuit compares the selected reference value to a first match value.

Claims

1. A method of controlling a device, the method comprising;

a first circuit receiving a first plurality of reference values;

the first circuit selecting a reference value from the first plurality according to a first reference identifier (ID) that is stored in memory;

the first circuit comparing the selected reference value to a first match value.

2. The method of claim 1 further comprising an act of switching a state of a first signal from inactive to active if the first match value compares equally to or less than the selected reference value.

3. The method of claim 2 further comprising:

the first circuit receiving a second plurality of reference values after the first circuit receives the first plurality of reference values;

the first circuit selecting a reference value from the second plurality according to the first reference ID;

the first circuit comparing the first match value to the reference value that was selected from the second plurality;

switching the first signal state from inactive to active if the first match value compares equally to or less than the reference value that was selected from the second plurality.

4. The method of claim 3 further comprising:

switching the first signal state from inactive to active in response to comparing the first match value to the reference value selected that was selected from the second plurality;

the first circuit receiving a third plurality of reference values after the first circuit receives the second plurality of reference values;

the first circuit selecting a reference value from the third plurality according to a second reference ID that is stored in memory;

the first circuit comparing a second match value to the reference value that was selected from the third plurality.

5. The method of claim 4 further comprising an act of switching the first signal state from active to inactive if the second match value compares equally or less than the reference value that was selected from the third plurality.

6. The method of claim 5 further comprising:

switching the first signal state from active to inactive in response to comparing the second match value to the reference value that was selected from the third plurality;

the first circuit receiving a fourth plurality of reference values after the first circuit receives the third plurality of reference values;

the first circuit selecting a reference value from the fourth plurality according to a third reference ID that is stored in memory;

the first circuit comparing a third match value to the reference value that was selected from the fourth plurality;

switching the first signal state from inactive to active if the third match value compares equally to or less than the reference values that was selected from the fourth plurality.

7. The method of claim 1 further comprising:

a processor receiving first data relating to one or more operational aspects of the motor;

the processor generating the first match value as a function of the first data;

the processor transmitting the first match value and the first reference ID to the first circuit for storage therein.

8. The method of claim 4 further comprising:

a processor receiving first data relating to one or more operational aspects of the motor;

the processor generating the first and second match values as a function of the first data;

the processor transmitting the first match value, the second match value, the first reference ID, and the second reference ID to the first circuit for storage therein before the first circuit receives the first plurality of reference values.

9. The method of claim 4 wherein the first and second reference IDs are identical.

10. The method of claim 4 wherein the first and second reference IDs are distinct from each other.

11. The method of claim 1 further comprising:

a second circuit receiving the first plurality of reference values;

the second circuit selecting another reference value from the first plurality according to a second reference ID that is stored in memory;

the second circuit comparing the other selected reference value to a second match value.

12. The method of claim 11 further comprising:

switching a state of a first signal from inactive to active if the first match value compares equally to or less than the selected reference value;

switching a state of a second signal from inactive to active if the second match value compares equally to or less than the other selected reference value.

13. The method of claim 12 further comprising:

activating a first actuator of the motor if the first signal state is switched from inactive to active;

activating a second actuator of the motor if the second signal state is switched from inactive to active.

14. The method of claim 11 further comprising:

switching a state of a first signal from inactive to active if the first match value compares equally to or less than the reference value;

switching a state of a second signal from inactive to active if the second match value compares equally to or less than the other reference value, or if the first signal state switches from the inactive state to the active state.

15. The method of claim 11 further comprising:

switching a state of a first signal from inactive to active if the first match value compares equally to or less than the reference value;

switching a state of a second signal from inactive to active if the second match value compares equally to or less than the other reference value, and if the first signal is in the inactive state.

16. A method comprising:

a first circuit receiving a first plurality of reference values;

the first circuit selecting a first reference value from the first plurality of reference values;

the first circuit comparing the selected first reference value to a first match value that is stored in memory;

a second circuit receiving the first plurality of reference values;

the second circuit selecting a second reference value from the first plurality of reference values, wherein the first and second reference values are distinct from each other;

the second circuit comparing the selected second reference value to a second match value that is stored in memory, wherein the first and second match values are distinct from each other.

17. An apparatus comprising for controlling a motor:

one or more first memory devices for receiving and storing a plurality of reference values;

a first reference selection circuit coupled to the one or more first memory devices, wherein the first circuit is configured to select a reference value from the plurality according to a reference ID that is stored in memory;

a first comparator circuit coupled to the first reference selection circuit, wherein the first comparator is configured to receive and to compare the selected reference value to a match value, and wherein the first comparator circuit is configured to assert a first match-signal in response to comparing the selected reference value to the match value.

18. The apparatus of claim 17 further comprising a first circuit coupled to the first comparator circuit, wherein the first circuit is configured to switch a state of a first signal from inactive to active or from active to inactive in response to the first comparator circuit generating the first match-signal.