Error Resilience Methods for Multi-Protocol Encapsulation Forward Error Correction Implementations

• US 20100115379A1
• Filed: 11/05/2009
• Published: 05/06/2010
• Est. Priority Date: 01/17/2006
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Gubbi, Rajugopal, Valmiki, Ramanujan
• Granted Patent: US 8,335,969 B2
• Time in Patent Office: Days
• US Class Current: 714/776
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/154 Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial
• CPC Class Codes: H03M 13/2707 Simple row-column interleaver, i.e. pure block interleaving
• CPC Class Codes: H03M 13/373 with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/4425 Monitoring of client processing errors or hardware failure
• CPC Class Codes: H04N 21/6112 involving terrestrial transmission, e.g. DVB-T
• CPC Class Codes: H04N 21/64315 DVB-H

Abstract

Systems, devices, and methods for error detection and correction in digital communication are disclosed. One such method comprises: storing data received in TS packets into an MPE-FEC frame buffer of a receiver according to locations indicated by an MPE-FEC frame buffer write pointer; and storing reliability information regarding said data separately therefrom, said reliability information including addresses of one or more locations in said MPE-FEC frame buffer to be marked for erasure. One such device is a receiver comprising an MPE-FEC frame buffer and an FEC decoder. The FEC decoder is configured to store data received in TS packets into the MPE-FEC buffer according to locations indicated by an MPE-FEC frame buffer write pointer. The FEC decoder is further configured to store reliability information regarding the data separately therefrom, the reliability information including addresses of one or more locations in the MPE-FEC frame buffer to be marked for erasure.

Claims

1. A method, comprising:

storing data received in TS packets into an MPE-FEC frame buffer of a receiver according to locations indicated by an MPE-FEC frame buffer write pointer; and

storing reliability information regarding said data separately therefrom, said reliability information including addresses of one or more locations in said MPE-FEC frame buffer to be marked for erasure.

2. The method of claim 1, wherein the reliability information comprises a starting address of a block of the data to be marked for erasure and an erasure flag.

3. The method of claim 2, wherein only non-erroneous data from the TS packets is stored into the MPE-FEC frame buffer, and further comprising moving the non-erroneous data corresponding to an MPE section to corresponding address locations within the MPE-FEC frame buffer so as to leave appropriate positions within the MPE-FEC frame buffer available for corrected data.

4. The method of claim 3, further comprising correcting data bytes stored at locations of the MPE-FEC frame buffer marked for erasure according to the reliability information using Reed-Solomon parity data stored in the MPE-FEC frame buffer.

5. The method of claim 4, further comprising writing back to the MPE-FEC frame buffer, at the locations marked for erasure according to the reliability information, the data bytes corrected using the Reed-Solomon parity data.

6. A receiver, comprising:

an MPE-FEC frame buffer; and

an FEC decoder configured to store data received in TS packets into the MPE-FEC buffer according to locations indicated by an MPE-FEC frame buffer write pointer, and further configured to store reliability information regarding the data separately therefrom, the reliability information including addresses of one or more locations in the MPE-FEC frame buffer to be marked for erasure.

7. The receiver of claim 6, wherein the reliability information comprises a starting address of a block of the data to be marked for erasure and an erasure flag.

8. The receiver of claim 6, wherein only non-erroneous data from the TS packets is stored into the MPE-FEC frame buffer, and wherein the FEC decoder is further configured to move the non-erroneous data corresponding to an MPE section to corresponding address locations within the MPE-FEC frame buffer so as to leave appropriate positions within the MPE-FEC frame buffer available for corrected data.

9. The receiver of claim 6, wherein the FEC decoder is further configured to correct data bytes stored at locations of the MPE-FEC frame buffer marked for erasure according to the reliability information using Reed-Solomon parity data stored in the MPE-FEC frame buffer.

10. The receiver of claim 7, further comprising writing back to the MPE-FEC frame buffer, at the locations marked for erasure according to the reliability information, the data bytes corrected using the Reed-Solomon parity data.