TRENCH SHIELDING STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD

• US 20100123220A1
• Filed: 11/14/2008
• Published: 05/20/2010
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Venkatraman, Prasad, Pratt, Brian, Burke, Peter A.
• Granted Patent: US 8,552,535 B2
• Time in Patent Office: Days
• US Class Current: 257/630
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.

Claims

1. A semiconductor device structure comprising:

a region of semiconductor material having a first major surface;

a first trench structure formed in an active area of the semiconductor device, wherein the first trench structure includes a first trench, a first control electrode, and a first shield electrode;

a control pad formed overlying the first major surface and coupled to the first control electrode; and

a second trench structure formed in the region of semiconductor material underlying at least a portion of the control pad, wherein the second trench structure includes a second trench, an insulator layer and a second shield electrode, and wherein the second shield electrode and the first shield electrode are coupled together, and wherein the second trench structure is configured as a shielding structure to isolate the control pad from the region of semiconductor material.

2. The structure of claim 1, wherein the second trench structure includes a plurality of trenches, wherein the plurality of trenches has a trench spacing less than about 0.3 microns.

3. The structure of claim 1, wherein the structure is absent any intervening conductive layers between the second trench structure and the control pad.

4. The structure of claim 1, wherein the second trench structure is formed absent a control electrode.

5. The structure of claim 1 further comprising a first control runner connecting the control pad to the first control electrode, wherein the second trench structure is further formed underlying at least a portion of the first control runner.

6. The structure of claim 1, wherein the second trench extends from a first side of the control pad to another side of the control pad opposite to the first side.

7. The structure of claim 1, wherein the first and second shield electrodes are coupled together with a shield electrode runner overlying the first major surface.

8. The structure of claim 7, wherein the second shield electrode does not overlap the first major surface, and wherein the shield electrode runner makes contact to the second shield electrode inside of the second trench.

9. The structure of claim 1, wherein the second trench structure includes a plurality of trenches each having a depth, wherein the plurality of trenches are spaced a distance less than about one-half the depth.

10. The structure of claim 1, wherein the control pad makes direct contact to the first control electrode underneath a portion of the control pad.

11. The structure of claim 1 further comprising a dielectric layer between the control pad and the second trench structure.

12. A semiconductor device structure comprising:

a region of semiconductor material having a major surface and first and second opposing edges;

a first trench formed in the region of semiconductor material extending in a direction from the first edge to the second edge;

a first shield electrode formed in the first trench;

a first control electrode formed in the first trench;

a second trench formed in the region of semiconductor material;

an insulator layer formed in the second trench;

a second shield electrode formed in the second trench overlying the insulator layer;

a control pad overlying at least a portion of the second trench, wherein the control pad is coupled to the first control electrode; and

a first shield electrode runner formed overlying the major surface, wherein the first shield electrode runner is coupled to the second shield electrode.

13. The structure of claim 12, wherein the first shield electrode is coupled to the second shield electrode adjacent the first edge, and wherein the structure further comprises a second shield electrode runner coupled to the second shield electrode adjacent the second edge.

14. The structure of claim 12 further comprising:

a control electrode runner connecting the control pad to the first control electrode;

a third trench formed in the region of semiconductor material below at least a portion of the control electrode runner; and

a third shield electrode formed in the third trench, wherein the second and third trenches are formed absent control electrodes.

15. The structure of claim 14 further comprising a dielectric layer overlying the second and third trenches, wherein the control pad overlies the dielectric layer.

16. A semiconductor device structure comprising:

a region of semiconductor material having a first major surface;

a first trench structure formed in an active area of the semiconductor device, wherein the first trench structure includes a first trench, a first control electrode, and a first shield electrode;

a control pad formed overlying the first major surface and coupled to the first control electrode;

a second trench structure formed in the region of semiconductor material underlying at least a portion of the control pad, wherein the second trench structure includes a second trench, an insulator layer and a second shield electrode, and wherein the second shield electrode and the first shield electrode are coupled together, and wherein the second trench structure is formed absent a control electrode; and

a dielectric layer formed between the control pad and the second trench structure.

17. The structure of claim 16, wherein the second trench structure includes a plurality of trenches each having a depth, wherein the plurality of trenches are spaced a distance less than about one-half the depth.

18. The structure of claim 16 further comprising a first control runner connecting the control pad to the first control electrode, wherein the second trench structure is further formed underlying at least a portion of the first control runner.

19. The structure of claim 16, wherein the structure is formed absent any conductive layers overlying the major surface between the control pad and the second trench structure.

20. The structure of claim 16, wherein the first shield electrode is coupled to the second shield electrode with a first shield electrode runner adjacent the first edge, and wherein the structure further comprises a second shield electrode runner coupled to the second shield electrode adjacent the second edge.

21. A method of forming a semiconductor device comprising the steps of:

providing a region of semiconductor material having a major surface and first and second opposing edges;

forming a first trench in the region of semiconductor material extending in a direction from the first edge to the second edge;

forming a first shield electrode in the first trench;

forming a first control electrode in the first trench;

forming a second trench in the region of semiconductor material;

forming an insulator layer in the second trench;

forming a second shield electrode in the second trench overlying the insulator layer;

forming a control pad overlying at least a portion of the second trench, wherein the control pad is coupled to the first control electrode; and

forming a first shield electrode runner overlying the major surface, wherein the first shield electrode runner is coupled to the second shield electrode.