Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias

• US 20100133704A1
• Filed: 12/01/2008
• Published: 06/03/2010
• Est. Priority Date: 12/01/2008
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Heng, Kock Liang, Marimuthu, Pandi Chelvam, Suthiwongsunthorn, Nathapong, Shim, Il Kwon
• Granted Patent: US 7,838,337 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13118 : Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/2518 : being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/9222 : Sequential connecting processes
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure.

Claims

1. A method of making a semiconductor device, comprising:

providing a carrier for supporting the semiconductor device;

mounting a first semiconductor die to the carrier, the first semiconductor die having a contact pad;

mounting a first dummy die to the carrier, the first dummy die having a through-silicon via (TSV);

encapsulating the first semiconductor die and the first dummy die using a wafer molding material;

forming a first interconnect structure over the first semiconductor die and the first dummy die, the first interconnect structure being connected to the contact pad of the first semiconductor die and the TSV of the first dummy die;

removing the carrier;

forming a second interconnect structure over the first semiconductor die and the first dummy die, the second interconnect structure being connected to the TSV of the first dummy die; and

connecting a semiconductor package to the second interconnect structure.

2. The method of claim 1, including:

forming a TSV in the first semiconductor die;

mounting a second semiconductor die over the first semiconductor die, the second semiconductor die being connected to the TSV of the first semiconductor die; and

mounting a second dummy die over the first dummy die, the second dummy die being connected to the TSV of the first dummy die.

3. The method of claim 1, including connecting the first interconnect structure to a printed circuit board (PCB).

4. The method of claim 1, wherein connecting a semiconductor package to the second interconnect structure includes flip-chip mounting a second semiconductor die to the second interconnect structure.

5. The method of claim 4, including thinning the encapsulant to expose a surface of the first semiconductor die and the first dummy die.

6. The method of claim 1, wherein the second interconnect structure includes a plurality of solder bumps.

7. The method of claim 1, wherein the first dummy die includes alignment markings to control placement of the first dummy die over the carrier.

8. A method of making a semiconductor device, comprising:

providing a carrier for supporting the semiconductor device;

mounting a first semiconductor die to the carrier;

mounting a first dummy die to the carrier, the first dummy die having a through-silicon via (TSV);

depositing encapsulant over the first semiconductor die and the first dummy die;

forming a first interconnect structure over the first semiconductor die and the first dummy die, the first interconnect structure being connected to the first semiconductor die and the TSV of the first dummy die;

removing the carrier; and

forming a second interconnect structure over the first semiconductor die and the first dummy die, the second interconnect structure being connected to the TSV of the first dummy die.

9. The method of claim 8, including connecting a semiconductor package to the second interconnect structure.

10. The method of claim 9, wherein connecting a semiconductor package to the second interconnect structure includes flip-chip mounting a second semiconductor die to the second interconnect structure.

11. The method of claim 8, including:

forming a TSV in the first semiconductor die;

mounting a second semiconductor die over the first semiconductor die, the second semiconductor die being connected to the TSV of the first semiconductor die; and

mounting a second dummy die over the first dummy die, the second dummy die being connected to the TSV of the first dummy die.

12. The method of claim 8, including thinning the encapsulant to expose a surface of the first semiconductor die and the first dummy die.

13. The method of claim 8, wherein the second interconnect structure includes a plurality of solder bumps.

14. The method of claim 8, wherein the first dummy die includes alignment markings to control placement of the first dummy die over the carrier.

15. The method of claim 8, including connecting the first interconnect structure to a printed circuit board (PCB).

16. A method of making a semiconductor device, comprising:

providing a carrier for supporting the semiconductor device;

mounting a first semiconductor device to the carrier;

mounting a second semiconductor device to the carrier, the second semiconductor device having a through-silicon via (TSV);

encapsulating the first and second semiconductor devices;

forming a first interconnect structure over the first semiconductor die and the first dummy die, the first interconnect structure being connected to the first semiconductor device and the TSV of the second semiconductor device; and

forming a second interconnect structure over the first and second semiconductor devices, the second interconnect structure being connected to the TSV of the second semiconductor device.

17. The method of claim 16, wherein the second semiconductor device includes alignment markings to control placement of the second semiconductor device over the carrier.

18. The method of claim 16, including connecting a semiconductor package to the second interconnect structure.

19. The method of claim 18, wherein connecting a semiconductor package to the second interconnect structure includes flip-chip mounting a second semiconductor die to the second interconnect structure.

20. The method of claim 19, including connecting the first interconnect structure to a printed circuit board (PCB).

21. A semiconductor device, comprising:

a first semiconductor die;

a first dummy die mounted to the carrier proximate to the first semiconductor die, the first dummy die having a through-silicon via (TSV);

encapsulant deposited over the first semiconductor die and the first dummy die;

a first interconnect structure formed over the first semiconductor die and the first dummy die, the first interconnect structure being connected to the first semiconductor die and the TSV of the first dummy die; and

a second interconnect structure formed over the first semiconductor die and the first dummy die, the second interconnect structure being connected to the TSV of the first dummy die.

22. The semiconductor device of claim 21, including a semiconductor package connected to the second interconnect structure.

23. The semiconductor device of claim 22, wherein the semiconductor package includes a second semiconductor die flip-chip mounted to the second interconnect structure.

24. The semiconductor device of claim 21, including:

a second semiconductor die mounted over the first semiconductor die, the second semiconductor die being electrically connected to the first semiconductor die; and

a second dummy die mounted over the first dummy die, the second dummy die being connected to the TSV of the first dummy die.

25. The semiconductor device of claim 21, wherein the first dummy die includes alignment markings to control placement of the first dummy die over the carrier.