METHOD AND DEVICE FOR PROVIDING ELECTRONIC CIRCUITRY ON A BACKPLATE

• US 20100144230A1
• Filed: 02/22/2010
• Published: 06/10/2010
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Tyger, Karen
• Granted Patent: US 7,933,476 B2
• Time in Patent Office: Days
• US Class Current: 445/24
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: G09G 2300/04 Structural and physical details of display devices
• CPC Class Codes: G09G 3/3466 based on interferometric effect
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A MEMS-based display device is described, wherein an array of interferometric modulators are configured to reflect light through a transparent substrate. The transparent substrate is sealed to a backplate and the backplate may contain electronic circuitry fabricated on the backplane. The electronic circuitry is placed in electrical communication with the array of interferometric modulators and is configured to control the state of the array of interferometric modulators.

Claims

1. A method of fabricating a display, comprising:

providing a transparent substrate comprising an array of interferometric modulators on a first surface of the transparent substrate, wherein said modulators comprise reflective elements;

providing a backplate having a first surface;

forming electronic circuitry on the first surface of the backplate, wherein the electronic circuitry is configured to control the state of said reflective elements; and

positioning the transparent substrate and the backplate such that the first surface of the transparent substrate is located proximal the first surface of the backplate and the electronic circuitry is placed in electrical connection with the array of interferometric modulators.

2. The method of claim 1, wherein the electronic circuitry is formed by thin film deposition.

3. The method of claim 1, further comprising depositing a first conducting material in electric connection with the array of interferometric modulators and depositing a second conducting material in electric connection with the electronic circuitry, said depositing of said first and second conductive material being done prior to the positioning of the transparent substrate and the backplate relative to one another.

4. The method of claim 3, wherein said first conducting material is deposited on said array of interferometric modulators and second conducting material is deposited on said first surface of the backplate.

5. The method of claim 3, wherein said first and second conducting materials comprise bumps of conducting material.

6. The method of claim 5, additionally comprising:

positioning said transparent substrate and said backplate such that said bumps of conducting material come into contact with one another; and

thermally compressing said transparent substrate and said backplate together, whereby the bumps are flattened.

7. The method of claim 5, additionally comprising:

depositing a layer of anisotropic conducting film such that it is in contact with either the first or second conducting material;

positioning said transparent substrate and said backplate such that said both said first and second conducting materials are in electrical contact with the layer of anisotropic conducting film; and

thermally compressing said transparent substrate and said backplate together.

8. The method of claim 2, wherein forming electronic circuitry on the first surface of the backplate comprises:

depositing a base layer of silicon on said first surface of said backplate; and

depositing a plurality of metal layers on said base layer of silicon.

9. The method of claim 8, wherein said deposition of said base layer of silicon and said plurality of metal layers is done via photolithography.

10. The method of claim 2, wherein forming electronic circuitry on the first surface of the backplate comprises:

forming transistors on the first surface of the backplate; and

forming metallic interconnections between the transistors.

11. The method of claim 10, wherein forming electronic circuitry on the first surface of the backplate further comprises:

forming metallic connections between the transistors and external electronic circuitry; and

forming metallic connections between the transistors and the array of interferometric modulators.

12. The method of claim 10, wherein forming transistors on the first surface of the backplate comprises:

depositing a layer of doped amorphous silicon on the transparent substrate;

implanting oppositely-doped silicon within the layer of doped amorphous silicon to form wells;

depositing a first layer of insulating material over the layer of amorphous silicon and the wells; and

depositing a gate above the first layer of insulating material, wherein the gate comprises electrically conductive material.

13. The method of claim 12, wherein forming transistors on the first surface of the backplate further comprises:

depositing a second layer of insulating material over the gate and the first layer of insulating material;

etching the first and second layers of insulating material to form conductive pathways through the layers of insulating material to the wells and gate; and

depositing a first metallic interconnect layer over the second layer of insulating material, the metallic interconnect layer extending through the conductive pathways.

14. The method of claim 13, further comprising forming metallic connections between the transistors and external circuitry, wherein forming metallic connections between the transistors and external circuitry comprises:

depositing a top metal layer above the first metallic interconnect layer; and

photolithographically etching the top metal layer to form the connections.

15. The method of claim 1, wherein the electronic circuitry comprises an application-specific integrated circuit (ASIC).

16. The method of claim 15, wherein the ASIC comprises a silicon layer.

17. A process of manufacturing a display comprising:

providing a transparent substrate having a first surface;

forming an array of interferometric modulators on the first surface of the transparent substrate, wherein said modulators comprise reflective elements;

providing a backplate having a first surface;

forming electronic circuitry on the first surface of the backplate, wherein the electronic circuitry is configured to control the state said reflective elements; and

positioning the transparent substrate and the backplate such that the first surface of the transparent substrate is located proximal the first surface of the backplate and the electronic circuitry is placed in electrical connection with the array of interferometric modulators.

18. The process of claim 17, wherein forming electronic circuitry on the first surface of the transparent substrate comprises:

photolithographically depositing a base layer of silicon on the first surface of the backplate; and

photolithographically depositing a plurality of metal layers on said base layer of silicon.

19. The process of claim 17, wherein forming electronic circuitry on the first surface of the transparent substrate comprises forming an application-specific integrated circuit comprising a silicon layer.