COMPILER IMPLEMENTATION OF LOCK/UNLOCK USING HARDWARE TRANSACTIONAL MEMORY

• US 20100146480A1
• Filed: 12/10/2008
• Published: 06/10/2010
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Song, Yonghong, Tirumalai, Partha P., Kalogeropulos, Spiros
• Granted Patent: US 8,612,929 B2
• Time in Patent Office: Days
• US Class Current: 717/106
• CPC Class Codes: G06F 8/458 Synchronisation, e.g. post-wait, barriers, locks synchronisation among tasks G06F9/52
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A system and method for automatic efficient parallelization of code combined with hardware transactional memory support. A software application may contain a transaction synchronization region (TSR) utilizing lock and unlock transaction synchronization function calls for a shared region of memory within a shared memory. The TSR is replaced with two portions of code. The first portion comprises hardware transactional memory primitives in place of lock and unlock function calls. Also, the first portion ensures no other transaction is accessing the shared region without disabling existing hardware transactional memory support. The second portion performs a fail routine, which utilizes lock and unlock transaction synchronization primitives in response to an indication that a failure occurs within said first portion.

Claims

1. A method comprising:

examining one or more program instructions;

identifying a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory;

replacing the TSR with a first portion of code and a second portion of code; and

setting an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution.

2. The method as recited in claim 1, wherein said TSR comprises lock and unlock transaction synchronization function calls, and wherein said first portion of code comprises a replacement command pair in place of the lock and unlock function calls.

3. The method as recited in claim 2, further comprising generating code for said first portion operable to ensure no other transaction is accessing said shared region without disabling existing hardware transactional memory support.

4. The method as recited in claim 3, wherein said code to ensure is operable to determine a predetermined safe value is stored in a predetermined memory location, wherein the predetermined memory location is accessible by both user-specified transactions and transactions within hardware transactional memory support.

5. The method as recited in claim 2, further comprising generating code for said second portion of code operable to perform a failure handling routine which utilizes lock and unlock transaction synchronization function calls, in response to an indication a failure occurs within said first portion.

6. The method as recited in claim 5, wherein setting said indication further comprises identifying one or more of the following:

the TSR comprises a predetermined instruction type, the TSR exceeds available space in a store buffer, and the TSR comprises more than a predetermined number of instructions.

7. The method as recited in claim 6, wherein setting said indication further comprises utilizing program profiling information.

8. The method as recited in claim 2, wherein said first portion of code comprises hardware transactional memory primitives.

9. A compiler comprising:

a processor core selection unit configured to assign software threads to waiting hardware threads;

a code generator; and

an optimizer, wherein the optimizer is configured to;

examine one or more program instructions;

identify a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory;

replace the TSR with a first portion of code and a second portion of code; and

set an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution.

10. The compiler as recited in claim 9, wherein said TSR comprises lock and unlock transaction synchronization function calls, and wherein the code generator is configured to generate said first portion of code to include a replacement command pair in place of the lock and unlock function calls.

11. The compiler as recited in claim 10, wherein the code generator is configured to generate code for said first portion operable to ensure no other transaction is accessing said shared region without disabling existing hardware transactional memory support.

12. The compiler as recited in claim 11, wherein said code to ensure is operable to determine a predetermined safe value is stored in a predetermined memory location, wherein the predetermined memory location is accessible by both user-specified transactions and transactions within hardware transactional memory support.

13. The compiler as recited in claim 10, wherein the code generator is configured to generate code for said second portion operable to perform a failure handling routine which utilizes lock and unlock transaction synchronization function calls, in response to an indication a failure occurs within said first portion.

14. The compiler as recited in claim 13, wherein the optimizer, in order to set said indication, is operable to identify one or more of the following:

the TSR comprises a predetermined instruction type, the TSR exceeds available space in a store buffer, and the TSR comprises more than a predetermined number of instructions.

15. The compiler as recited in claim 14, wherein the optimizer, in order to set said indication, utilizes program profiling information.

16. The compiler as recited in claim 10, said first portion of code comprises hardware transactional memory primitives.

17. A computer readable storage medium storing program instructions operable to parallelize code combined with hardware transactional memory support, wherein the program instructions are executable to:

examine one or more program instructions;

identify a transaction synchronization region (TSR) within said program instructions, wherein the TSR accesses a shared region of memory within a shared memory;

replace the TSR with a first portion of code and a second portion of code; and

set an indication that the first portion of code is to be executed, in response to predicting the TSR will not fail during execution.

18. The storage medium as recited in claim 17, wherein said TSR comprises lock and unlock transaction synchronization function calls, and wherein said first portion of code comprises a replacement command pair in place of the lock and unlock function calls.

19. The storage medium as recited in claim 18, wherein the program instructions are further executable to generate code for said first portion operable to ensure no other transaction is accessing said shared region without disabling existing hardware transactional memory support.

20. The storage medium as recited in claim 18, wherein the program instructions are further executable to generate code for said second portion of code operable to perform a failure handling routine which utilizes lock and unlock transaction synchronization function calls, in response to an indication a failure occurs within said first portion.