Miniaturized implantable sensor platform having multiple devices and sub-chips

• US 20100148293A1
• Filed: 11/16/2009
• Published: 06/17/2010
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: Faquir Chand Jain, Fotios Papadimitrakopulos
• Original Assignee: Faquir Chand Jain, Fotios Papadimitrakopulos
• Inventors: Papadimitrakopulos, Fotios, Jain, Faquir Chand
• Granted Patent: US 8,390,047 B2
• Time in Patent Office: Days
• US Class Current: 257/434
• CPC Class Codes: A61B 2560/0214 of power generation or supply
• CPC Class Codes: A61B 2562/12 Manufacturing methods specially adapted for producing sensors for in-vivo measurements
• CPC Class Codes: A61B 5/0017 transmitting optical signals transmission by light H04B10/00
• CPC Class Codes: A61B 5/0031 Implanted circuitry
• CPC Class Codes: A61B 5/14532 for measuring glucose, e.g. by tissue impedance measurement
• CPC Class Codes: A61B 5/1473 invasive, e.g. introduced into the body by a catheter A61B5/1482 takes precedence
• CPC Class Codes: A61B 5/6846 specially adapted to be brought in contact with an internal body part, i.e. invasive
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 31/02005 for device characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/048 Encapsulation of modules
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

An implantable, miniaturized platform and a method for fabricating the platform is provided, where the e platform includes a top cover plate and a bottom substrate, top cover plate including an epitaxial, Si-encased substrate and is configured to include monolithically grown devices and device contact pads, the Si-encased substrate cover plate including a gold perimeter fence deposited on its Si covered outer rim and wherein the bottom substrate is constructed of Si and includes a plurality of partial-Si-vias (PSVs), electronic integrated circuits, device pads, pad interconnects and a gold perimeter fence, wherein the device pads are aligned with a respective device contact pad on the top cover plate and includes gold bumps having a predetermined height, the top cover plate and the bottom substrate being flip-chip bonded to provide a perimeter seal and to ensure electrical connectivity between the plurality of internal devices and at least one external component.

Claims

1. A device platform, which contains at least one internal component, wherein the device platform is configured to isolate the at least one internal component from an environment external to the device platform while providing for electrical connectivity to at least one external component externally located on the outer surface of the said device platform, the device comprising:

an enclosure, said enclosure including a top cover plate and a bottom substrate configured to define a sealed enclosure cavity for containing the at least one component,

wherein said top cover plate is configured to allow reception and transmission of electromagnetic radiation, the surface of said top cover plate adjacent said enclosure cavity being covered with an epitaxial Si film in intimate cohesion, and

wherein said bottom substrate is constructed of a high resistivity Si having a Si substrate material conductivity and includes at least one partial Si via (PSV), wherein said at least one partial Si via (PSV) is configured to electrically connect said at least one internal component with said at least one external component, and

wherein said partial Si via (PSV) is formed by introducing a dopant with said Si material, wherein the combination of said dopant and said Si material results in at least one of a reduced conductivity and a conductivity that is opposite to that of said Si substrate material conductivity, and

wherein an outer perimeter of each of said surface of said top cover plate adjacent said enclosure cavity and a surface of said bottom substrate adjacent said enclosure cavity includes a continuous gold fence cohesively bonded to its respective Si surface, wherein said top cover plate and said bottom substrate are configured such that said enclosure cavity is sealed using a gold-to-gold bond.

2. The device of claim 1, wherein said at least one internal component includes a plurality of components, and wherein said at least one external component includes a plurality of components, and wherein said at least one partial Si via (PSV) includes a plurality of partial Si vias (PSVs), each of said plurality of partial Si vias (PSVs) being electrically isolated from each other and electrically connected to one of said plurality of internal and external components.

3. The device of claim 2, wherein said external component is a biosensor.

4. The device of claim 3, wherein the said biosensor is selected from electrochemical biosensor and chemical field effect transistors (Chem-FETs).

5. The device of claim 1, wherein said device is miniaturized to fit inside of a hypodermic needle.

6. The device of claim 1, wherein said top cover plate is constructed from at least one of an epitaxial Si film on sapphire material, an epitaxial Si film-on-quartz material, an epitaxial Ge film-on-ZnSe material, an epitaxial Si film on ZnS material and an epitaxial Si film on SiC material.

7. The device of claim 1, wherein said at least one partial Si via (PSV) is formed by at least one of,

diffusing n-type dopants into a p-type substrate having a high resistivity,

implanting n-type dopants into a p-type substrate and performing thermal annealing to remove lattice damage,

diffusing p-type dopants into an n-type substrate having a high resistivity,

implanting n-type dopants into a p-type substrate and performing thermal annealing to remove lattice damage, and

diffusing p-type dopants into a p-Si substrate having a high resistivity, and isolating said diffused regions by surrounding them with ion implanted box oxide.

8. The device of claim 1, wherein said partial Si vias (PSVs) are isolated from each other by surrounding them with ion implanted box oxide.

9. The device of claim 1, wherein said at least one internal component includes at least one photodetector and at least one photovoltaic cell contained within said enclosure cavity such that electromagnetic energy transmitted through at least one predetermined region of said top cover plate is incident upon said at least one photodetector and at least one photovoltaic cell, wherein said epitaxial Si film may be removed to enhance radiation transmission through said predetermined regions.

10. The device of claim 9, wherein said at least one component further includes a signal processing device, wherein said signal processing device is connected with said at least one photovoltaic cell using at least two photovoltaic cell interconnects and wherein said signal processing device is connected with said at least one photodetector using at least two photodetector interconnects, wherein said photovoltaic cell interconnects and said photodetector interconnects are created by patterning said epitaxial Si film on said surface of said top cover plate within said enclosure cavity, where said photovoltaic cell interconnects and said photodetector interconnects are constructed from a material having low electrical resistivity.

11. The device of claim 10, wherein said at least one photovoltaic cell interconnect and said at least one photodetector interconnect are constructed from at least one of gold, silver, aluminum, palladium, platinum and copper.

12. The device of claim 1, wherein said enclosure further includes at least one Si spacer located between said top cover plate and said bottom substrate to define a sealed enclosure cavity for containing the at least one component, wherein the outer perimeter of said at least one spacer also includes a continuous gold fence bonded cohesively to its respective Si surface and wherein when said at least one Si spacer, said top cover plate and said bottom substrate form said enclosure cavity, said continuous gold fence on said top cover plate is gold-to-gold bonded to said continuous gold fence on said top surface of said at least one spacer and said continuous gold fence on said bottom substrate is bonded to said continuous gold fence on said bottom surface of said at least one spacer to seal said enclosure cavity.

13. The device of claim 12 where the said spacer is a patterned gold perform with similar dimensions as the gold fence.

14. The device of claim 1 wherein said cohesive bonding is achieved by the formation Au—

Si eutectic.

15. The device of claim 1, wherein cohesively bonding between Si and gold is achieved by the formation of a silicide.

16. The device of claim 15, wherein said silicide includes at least one of Molybdenum, Palladium, Platinum, Titanium, and Nickel.

17. The device of claim 1, wherein said top cover plate includes a polycrystalline Si film on a substrate which includes at least one of glass, quartz, AlN, SiC, sapphire, ZnS ZnSe, and ZnO.

18. The device of claim 1, wherein said top cover plate is constructed from a glass substrate and a Si wafer, where said glass substrate is bonded to said Si wafer, wherein said Si wafer is thinned.

19. A method for integrating a plurality of device into a device platform, the method comprising:

forming the device platform using a top cover plate and a bottom substrate separated by at least one Si spacer, wherein said device platform defines a device cavity and said top cover plate is configured to allow electromagnetic radiation to be transmitted through said top cover plate, wherein a portion of said top cover plate includes an epitaxial Si film constructed from at least one of Si-on-Sapphire and Si-on-Quartz;

patterning and depositing a gold film on said epitaxial Si film to create a Si—

Au eutectic perimeter fence, at least one interconnect, at least one contact pad and at least one mounting pad for securing and interconnecting at least one internal component located within said device cavity, said at least one internal component including at least one of a photovoltaic cell and a photodetector, wherein said bottom substrate is constructed of a high resistivity Si substrate material,

wherein said bottom substrate includes a signal processing device and a light emitting diode serving as an optical transmitter, wherein said bottom substrate includes bonding pads and interconnects deposited on a patterned insulating layer of grown or deposited oxide,

wherein said bottom substrate has a plurality of partial Si vias (PSV) for electrically connecting at least one of said internal components with at least one device located on an outer surface of the bottom substrate,

wherein said plurality of partial Si vias (PSVs) are electrically isolated from each other and are formed by introducing a dopant having an opposite conductivity to that of said high resistivity Si substrate,

wherein said bottom substrate hosts a plurality of bottom substrate pads and said cover plate host a plurality of cover plate pads, wherein said bottom substrate pads and said cover plate pads are aligned with each other and include gold bumps of varying height to permit connectivity between components located on the cover plate and said signal processing device and said light emitting diode,

wherein the Si side of said cover plate, top and bottom surfaces of said at least one Si spacer and a top side of said bottom substrate are deposited with a continuous gold fence on an outer perimeter, wherein one side of said gold fence is bonded to a Si surface forming a gold-Si eutectic mixture and wherein an opposing side of said gold fence is bonded to a like gold fence using a gold-to-gold bond to seal said device platform.

20. The method of claim 19, wherein said gold-to-gold bonding between said gold fences also enable the formation of respective gold bump to gold bump bonding to provide electrical connectivity between said components located on said cover plate and said components located on the bottom substrate.

21. The method of claim 19, wherein the said device platform is sealed such as to protect internal component from long-term exposure to moisture, oxygen, body fluids and corrosive environments.

22. The method of claim 19, wherein the said device located on an outer surface is comprised of a list of a biosensor, chemical sensor, nuclear radiation detecting sensor, temperature sensor, and pressure sensor.

23. The method of claim 19, where the said gold-to-gold bonding is performed using flip-chip thermocompression and thermosonic bonding techniques.

24. The method of claim 19, where at least one interconnect is realized by a wire bond.

25. The method of claim 19, wherein said top cover plate is constructed from at least one of an epitaxial Si film on sapphire material, an epitaxial Si film-on-quartz material, an epitaxial Ge film-on-ZnSe material, an epitaxial Si film on ZnS material and an epitaxial Si film on SiC material.

26. The method of claim 19, wherein said partial Si vias (PSVs) are formed in said high resistivity bottom substrate using at least one of,

diffusing n-type dopants into a p-type substrate having a high resistivity,

implanting n-type dopants into a p-type substrate and performing thermal annealing to remove lattice damage,

diffusing p-type dopants into an n-type substrate having a high resistivity, and

implanting n-type dopants into a p-type substrate and performing thermal annealing to remove lattice damage, and

diffusing p-type dopants into a p-Si substrate having a high resistivity, and isolating said diffused regions by surrounding them with ion implanted box oxide.

27. The method of claim 19, wherein said spacer is cohesively bonded with said top cover plate and said bottom Si substrate using a silicide.

28. The method of claim 27, wherein said silicide includes at least one of Palladium, Platinum Titanium, and Nickel.

29. The method of claim 19, wherein said gold bumps on said plurality of pads are constructed from at least of indium, indium alloys, tin and silver, and wherein said gold bumps are of varying height to permit connectivity between said partial-Si-vias (PSVs), said at least one component and said signal processing device.

30. The method of claim 19, wherein the said photovoltaic cells, photodetectors, and light emitting devices are monolithically grown on the said epitaxial Si film on the top cover plate.

31. The method of claim 19, wherein the said signal processing device is monolithically grown on the said high resistivity Si bottom substrate.

32. The method of claim 19, wherein the said spacer is another high resistivity substrate, said spacer substrate has a perimeter fence on either sides, said spacer substrate contains partial-Si-vias, through-Si-vias (TSVs), etched holes, electronic and optoelectronic internal components, interconnects pads, wire bonds and mounting pads for securing various internal components.

33. A miniaturized device platform, the miniaturized device platform comprising:

a first substrate and a second substrate configured to form an enclosure, said second substrate being constructed from a high-resistivity semiconductor material, wherein the miniaturized device platform is immersed in a corrosive and high temperature external environment, said enclosure housing a plurality of internal components and being configured to isolate said plurality of components from said external environment, said miniaturized device platform configured to allow reception and transmission of electromagnetic radiation through at least one of said first substrate and said second substrate, wherein said enclosure includes a plurality of partial-semiconductor-vias (PSVs) configured to electrically connect at least one of said plurality of internal components with an external component, wherein said partial-semiconductor-vias (PSemVs) are constructed on a thinned section of said second substrate and are created by introducing an impurity to said second substrate, the combination of said second substrate and said impurity configured to provide electrical conductivity, wherein said first substrate and said second substrate are cohesively sealed using a combination of at least one of an epitaxial interface, a eutectic mixture, a metal silicide, and a metal to metal bond.

34. The miniaturized device platform of claim 33, wherein said plurality of internal components includes at least one of an electronic device, an optoelectronic device, an integrated circuit device, a battery, micromechanical device, an ultrasound device, and a thermoelectric device

35. The miniaturized device platform of claim 33, wherein said outside components are comprised of a list of a biosensor, chemical sensor, nuclear radiation detecting sensor, temperature sensor, and pressure sensor.

36. The miniaturized device platform of claim 33, wherein said outside components are comprised of a list of a power generating devices selected of a list of biofuel cell, fuel cell, battery, thermoelectric generator, micro-electromechanical energy generators.

37. The miniaturized device platform of claim 33, wherein the said reception and transmission of electromagnetic radiation through one of its substrates establishes at least one wireless link with a central control unit.

38. The miniaturized device platform of claim 37, wherein said at least one wireless link includes repeated wireless links with multiple miniaturized device platforms to collectively establish a network of miniaturized device platforms, said network of miniaturized device platforms providing environmental information at different locations.