LIQUID CRYSTAL DISPLAY AND THIN FILM TRANSISTOR ARRAY PANEL THEREFOR

• US 20100149447A1
• Filed: 12/03/2009
• Published: 06/17/2010
• Est. Priority Date: 11/14/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LYU, Jae-Jin, UM, Yoon-Sung, LEE, Jung-Hee, SON, Jong-Ho
• Granted Patent: US 8,228,452 B2
• Time in Patent Office: Days
• US Class Current: 349/39
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and second drain electrodes; and first and second pixel electrodes electrically connected to the first and second electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.

Claims

1. A liquid crystal display, comprising:

a first panel including;

a first insulating substrate;

a plurality of gate lines provided on the first substrate;

a plurality of data lines provided on the first substrate;

a plurality of first thin film transistors connected to the gate lines and the data lines;

a plurality of second thin film transistor connected to the gate lines and the data lines;

a plurality of first pixel electrodes connected to the first thin film transistors; and

a plurality of second pixel electrodes connected to the second thin film transistors;

a second panel facing the first panel and including a second insulating substrate and a common electrode provided on the second substrate; and

a liquid crystal layer interposed between the first panel and the second panel and comprising a plurality of liquid crystal molecules,

wherein two different voltages originated from a single signal are applied to the first and second pixel electrodes,

wherein the first pixel electrode connects to a first electric capacitor and the second pixel electrode connects to a second electric capacitor, a capacitance of the first electric capacitor is different from a capacitance of the second electric capacitor,

wherein the first thin film transistor includes a first terminal, a second terminal, and a third terminal connected to the first pixel electrode and the second thin film transistor includes a first terminal, a second terminal, and a third terminal connected to the second pixel electrode,

wherein the third terminal of the first thin film transistor connects to a first storage capacitor and the third terminal of the second thin film transistor connects to a second storage capacitor, and

wherein the liquid crystal molecules are vertically aligned when the liquid crystal layer is not applied an electric field.

2. The liquid crystal display of claim 1, wherein a capacitance between the first terminal and the third terminal of the first thin film transistor is different from that between the first terminal and the third terminal of the second thin film transistor.

3. The liquid crystal display of claim 2, further comprising a first storage electrode line connected to the first storage capacitor and a second electrode line connected to the second storage capacitor.