IP STORAGE PROCESSOR AND ENGINE THEREFOR USING RDMA

• US 20100161750A1
• Filed: 10/21/2009
• Published: 06/24/2010
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Memory Access Technologies LLC
• Original Assignee: Ashish A. Pandya
• Inventors: Pandya, Ashish A.
• Granted Patent: US 7,870,217 B2
• Time in Patent Office: Days
• US Class Current: 709/212
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

An IP Storage processor and processing engines for use in the IP storage processor is disclosed. The IP Storage processor uses an architecture that may provide capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also perform packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache may store a transport protocol session information database and/or store a storage information session database, for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through ROMA data transfer.

Claims

1-63. -63. (canceled)

64. A programmable TCP/IP chip used for processing Internet Protocol packets in TCP/IP sessions in accordance with TCP/IP session information and configured to be coupled to one or more host processors of a host system, said one or more host processors for processing data transferred using said internet Protocol Packets, said host system comprising host buffers coupled to said one or more host processors, said programmable TCP/IP chip comprising:

a. a remote direct memory access (RDMA) capability for performing RDMA data transfers;

b. at least one network interface configured to send and/or receive said Internet Protocol packets from or to said TCP/IP chip;

c. a memory on said TCP/IP chip for storing said TCP/IP session information or said Internet Protocol packets;

d. a memory controller for controlling access to said memory for storing or retrieving said TCP/IP session information or said Internet Protocol packets.

e. a TCP checksum generator for checksum generation or verification or a combination thereof;

f. a TCP segmentation controller for performing TCP segmentation;

g. a TCP/IP header processing engine for processing or generating TCP/IP headers or fields;

h. a RDMA header processing engine for generating or processing RDMA headers or fields;

i. a transmit engine or a receive engine or a combination thereof for retrieving data from said host buffers or performing direct data placement or zero copy in said host buffers without substantial intervention by said one or more host processors;

j. an execution resource to perform TCP/IP operations on said Internet Protocol packets;

k. an execution resource to perform RDMA operations on said Internet Protocol packets that require RDMA processing; and

l. a host interface controller to couple said TCP/IP chip to said one or more host processors.

65. The programmable TCP/IP chip in accordance with claim 64, further comprising:

m. an iSCSI processing engine for offloading iSCSI processing from the said one or more host processors to perform iSCSI protocol data transfers;

n. a cyclic redundancy check engine for CRC verification or for new CRC generation;

or

o. a combination of the foregoing.

66. A programmable TCP/IP chip used for processing Internet Protocol packets and configured to be coupled to a host system, said host system comprising one or more host processors, said one or more host processors having access to host buffers, said TCP/IP chip comprising:

a. a memory for storing or retrieving said Internet Protocol Packets, or having access to a memory of said TCP/IP chip for storing or retrieving said Internet Protocol packets;

b. remote direct memory access (RDMA) capability for performing RDMA data transfers;

c. a RDMA engine for performing RDMA data transfers;

d. at least one network interface to send or receive said Internet Protocol packets;

e. a memory controller for controlling access to said memory on said TCP/IP chip or off said TCP/IP chip for storing or retrieving said Internet Protocol packets;

f. an execution resource to perform TCP/IP operations on said Internet Protocol packets comprising;

f1. a TCP checksum generator for checksum generation or verification or a combination thereof;

f2. a TCP segmentation controller for performing TCP segmentation;

f3. a TCP/IP header processing engine for processing or generating TCP/IP headers or fields; and

f4. a combination of any of f1, f2, and f3;

g. a transmit engine or a receive engine or combination thereof for retrieving data from said host buffers or performing direct data placement or zero copy in said host buffers without substantial intervention by said one or more host processors; and

h. a host interface controller configured to couple said TCP/IP chip to said one or more host processors.

67. The programmable TCP/IP chip in accordance with claim 66, further comprising:

i. an iSCSI processing engine for offloading iSCSI processing from said one or more host processors to perform iSCSI protocol data transfers;

j. a cyclic redundancy check engine for CRC verification or for new CRC generation;

or

k. a combination of the foregoing.

68. The programmable TCP/IP chip in accordance with claim 66 wherein said RDMA engine further comprises a RDMA header processing engine for generating or processing RDMA headers or fields.

69. The said RDMA engine in accordance with claim 66 further comprising an execution resource to perform RDMA operations on said Internet Protocol packets that require RDMA processing.

70. A programmable TCP/IP chip having remote direct memory access (RDMA) capability for processing Internet Protocol packets having TCP/IP headers and fields and RDMA headers and fields during TCP/IP sessions in accordance with TCP/IP session information, said TCP/IP chip having a memory for storing or retrieving said Internet Protocol Packets or said TCP/IP session information, and said TCP/IP chip configured to be coupled to a host system, said host system comprising one or more host processors and host buffers, said TCP/IP chip comprising:

a. a memory controller for controlling access to said memory for storing or retrieving said TCP/IP session information or said Internet Protocol packets;

b. a TCP/IP execution resource for generating or processing said TCP/IP header and field information and for performing TCP/IP operations on said Internet Protocol packets;

c. an RDMA execution resource for generating or processing said RDMA header and field information and for performing RDMA operations on said Internet Protocol packets that require RDMA operations; and

d. a transmit engine or a receive engine, or a combination thereof, coupled to one of said one or more host processors for retrieving data from said host buffers or performing direct data placement or zero copy in said host buffers without substantial intervention by said host processor.

71. The programmable TCP/IP chip in accordance with claim 70 further comprising an iSCSI processing engine for offloading iSCSI processing from said one or more host processors to perform iSCSI data transfers.

72. A host adapter comprising:

a programmable TCP/IP chip used for processing Internet Protocol packets in TCP/IP sessions in accordance with TCP/IP session information, said programmable TCP/IP chip comprising;

a. a remote direct memory access (RDMA) capability for performing RDMA data transfers;

b. at least one network interface configured to send and/or receive said Internet Protocol packets from or to said TCP/IP chip;

c. a memory on said TCP/IP chip for storing said TCP/IP session information or said Internet Protocol packets;

d. a memory controller for controlling access to said memory for storing or retrieving said TCP/IP session information or said Internet Protocol packets.

e. a TCP checksum generator for checksum generation or verification or a combination thereof;

f. a TCP segmentation controller for performing TCP segmentation;

g. a TCP/IP header processing engine for processing or generating TCP/IP headers or fields;

h. a RDMA header processing engine for generating or processing RDMA headers or fields;

i. a transmit engine or a receive engine or a combination thereof for retrieving data from host buffers or performing direct data placement or zero copy in said host buffers without substantial intervention by one or more host processors;

j. an execution resource to perform TCP/IP operations on said Internet Protocol packets;

k. an execution resource to perform RDMA operations on said Internet Protocol packets that require RDMA processing; and

l. a host interface controller to couple said TCP/IP chip to said one or more host processors.