MEMORY SYSTEM AND COMPUTER SYSTEM

• US 20100161937A1
• Filed: 12/22/2009
• Published: 06/24/2010
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Megachips Corporation
• Original Assignee: Megachips Corporation
• Inventors: TANAKA, Shinji
• Granted Patent: US 8,683,168 B2
• Time in Patent Office: Days
• US Class Current: 711/209
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A memory system of the present invention comprises a plurality of first blocks provided for storing user information therein, to which first physical addresses which are not duplicate are assigned, respectively, a plurality of second blocks provided for individually storing therein the first physical addresses of initial defective blocks out of the plurality of first blocks, and a plurality of third blocks provided for individually storing therein the first physical addresses of late defective blocks out of the plurality of first blocks. The memory system further comprises a computing device for obtaining the first physical address corresponding to a logical address on the basis of the logical address, information stored in the second blocks, and information stored in the third blocks.

Claims

1. A memory system comprising:

a plurality of first blocks provided for storing user information therein, to which first physical addresses which are not duplicate are assigned, respectively;

a plurality of second blocks provided for individually storing therein said first physical addresses of initial defective blocks out of said plurality of first blocks;

a plurality of third blocks provided for individually storing therein said first physical addresses of late defective blocks out of said plurality of first blocks; and

a computing device for obtaining said first physical address corresponding a logical address on the basis of said logical address, information stored in said second blocks, and information stored in said third blocks.

2. The memory system according to claim 1, wherein

said third blocks are assigned third physical addresses which are not duplicate, respectively, and

said first physical addresses of said late defective blocks to be stored in said third blocks are stored in said third blocks in the order of said third physical addresses in accordance with the order that late defects occur.

3. The memory system according to claim 2, wherein

said second blocks are assigned second physical addresses which are not duplicate, respectively, and

said first physical addresses of said initial defective blocks to be stored in said second blocks are stored in said second blocks in the order of said second physical addresses in accordance with the order of said first physical addresses.

4. The memory system according to claim 3, wherein

said computing device

(A) obtains said first physical address corresponding to said logical address on the basis of said logical address and said information stored in said second blocks, and

(B) determines if said first physical address obtained in said step (A) agrees with any one piece of said information stored in said third blocks.

5. The memory system according to claim 4, wherein

when said computing device determines in said step (B) that said first physical address agrees with one piece of said information stored in said third blocks, said computing device

(C) obtains an alternate logical address on the basis of said third physical address of said third block which stores therein said first physical address obtained in said step (A) and a leading alternate logical address which is prepared in advance, and

(D) obtains said first physical address corresponding to said logical address on the basis of said alternate logical address and said information stored in said second blocks.

6. The memory system according to claim 5, further comprising:

a first reserve block for storing said first physical address of said initial defective block out of said plurality of first blocks;

a second reserve block for storing said first physical address of said late defective block out of said plurality of first blocks; and

a transmission part for transmitting information stored in said first reserve block to said second block and transmitting information stored in said second reserve block to said third block.

7. The memory system according to claim 3, wherein

said computing device

(E) obtains said first physical address corresponding to said logical address on the basis of said logical address and said information stored in said second blocks,

(F) makes access to said first block designated by said first physical address obtained in said step (E) and as the result thereof, determines if said first block is said late defective block, and

(G) records said first physical address obtained in said step (E) into the leading one of said third blocks in which no information of said first physical address is stored when said first block is determined to be said late defective block in said step (F).

8. The memory system according to claim 7, wherein

said computing device

(H) obtains an alternate logical address on the basis of said third physical address of said third block and a leading alternate logical address which is prepared in advance after said step (G), and

(I) obtains said first physical address corresponding to said logical address on the basis of said alternate logical address and said information stored in said second blocks.

9. The memory system according to claim 5, wherein

said computing device

(J) determines if a first block designated by said first physical address obtained in said step (D) has a defect.

10. The memory system according to claim 8, wherein

said computing device

(J) determines if a first block designated by said first physical address obtained in said step (I) has a defect.

11. The memory system according to claim 9, wherein

when said computing device determines that said first block has a defect, said computing device

(K) records said first physical address obtained in said step (D) into the leading one of said second blocks in which no information of said first physical address is stored.

12. The memory system according to claim 10, wherein

when said computing device determines that said first block has a defect, said computing device

(K) records said first physical address obtained in said step (I) into the leading one of said second blocks in which no information of said first physical address is stored.

13. The memory system according to claim 11, wherein

said computing device

(L) obtains said first physical address corresponding to said logical address on the basis of said alternate logical address obtained in said step (C) and information stored in said second block after said step (K).

14. The memory system according to claim 12, wherein

said computing device

(L) obtains said first physical address corresponding to said logical address on the basis of said alternate logical address obtained in said step (H) and information stored in said second block after said step (K).

15. The memory system according to claim 7, further comprising

a transmission part for transmitting said information of said second blocks to a first management area which is constituted of one part of said first blocks and transmitting said information of said third blocks to a second management area which is constituted of the other part of said first blocks.

16. The memory system according to claim 13, further comprising

a transmission part for transmitting said information of said second blocks to a first management area which is constituted of one part of said first blocks and transmitting said information of said third blocks to a second management area which is constituted of the other part of said first blocks.

17. The memory system according to claim 14, further comprising

a transmission part for transmitting said information of said second blocks to a first management area which is constituted of one part of said first blocks and transmitting said information of said third blocks to a second management area which is constituted of the other part of said first blocks.

18. The memory system according to claim 15, wherein

said transmission part transmits said information of said first management area to said second blocks and transmits said information of said second management area to said third blocks before said computing device derives said first physical address corresponding to said logical address.

19. The memory system according to claim 18, wherein

said second blocks and said third blocks are held in a volatile memory.

20. A computer system comprising:

a computer for generating a logical address;

a memory having a plurality of first blocks provided for storing user information therein, to which first physical addresses which are not duplicate are assigned, respectively;

a controller memory having a plurality of second blocks provided for individually storing therein said first physical addresses of initial defective blocks out of said plurality of first blocks, to which second physical addresses which are not duplicate are assigned, respectively, and a plurality of third blocks provided for individually storing therein said first physical addresses of late defective blocks out of said plurality of first blocks, to which third physical addresses which are not duplicate are assigned, respectively; and

a computing device for obtaining said first physical address corresponding to said logical address received from said computer on the basis of said logical address, information stored in said second blocks, and information stored in said third blocks.