×

Channel Scan Logic

  • US 20100164898A1
  • Filed: 03/12/2010
  • Published: 07/01/2010
  • Est. Priority Date: 01/03/2007
  • Status: Active Grant
First Claim
Patent Images

1. Channel scan logic for controlling scanning functions of a sensor panel, comprising:

  • a clock generator configured to generate a clock signal based on one of a plurality timing parameters inputted into the clock generator;

    a stimulus signal divider operatively connected to the clock generator, the stimulus frequency divider configured to output a stimulus signal by dividing a the clock signal by a stimulus divide parameter;

    a count divider operatively connected to the clock generator, the count divider configured to divide the clock signal by a count divide parameter to produce a count clock signal;

    a counter operatively connected to the count divider, the counter configured to generate a plurality of incremented signals in response to the count clock signal;

    a demodulation look up table operatively connected to the counter, the demodulation look up table outputting a demodulation value corresponding to each of the plurality of incremented signals;

    a channel timing generator configured receive channel timing parameters and generate an analog channel control signal based on the channel timing parameters;

    a sensor address generator configured to receive sensor address parameters and generate a sensor address control signal based on the sensor address parameters; and

    delay logic operatively connected to the channel timing generator and the demodulation lookup table, the delay logic configured to generate delayed demodulation waveform signals and delayed analog to digital control signals.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×