Tessellator Whose Tessellation Time Grows Linearly with the Amount of Tessellation

• US 20100164954A1
• Filed: 12/31/2008
• Published: 07/01/2010
• Est. Priority Date: 12/31/2008
• Status: Abandoned Application

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Inventors: Sathe, Rahul P., Rosen, Paul A.
• Application Number:
  US12/347,114
• Publication Number:
  US 20100164954A1
• Time in Patent Office: Days
• US Class Current: 345/423
• CPC Class Codes: G06T 17/20 Finite element generation, e.g. wire-frame surface description, tesselation
• CPC Class Codes: H04N 19/29 involving scalability at the object level, e.g. video object layer [VOL]
• CPC Class Codes: H04N 19/36 Scalability techniques involving formatting the layers as a function of picture distortion after decoding, e.g. signal-to-noise [SNR] scalability

Abstract

In accordance with some embodiments, a tessellator may experience only a linear increase in tessellation time with increasing edge levels of detail. Conventionally, tessellators experience a non-linear or quadratic increase in tessellation time with increasing levels of detail. In some embodiments, the intervals and the triangulation of the inner tessellation may be pre-computed. Then at run time, the pre-computed values may be looked up for the applicable edge level of detail.

Claims

1. A method comprising:

performing a tessellation whose tessellation time increases linearly with increasing tessellation level of detail.

2. The method of claim 1 including using a software tessellator.

3. The method of claim 1 including pre-computing inner tessellation values for a plurality of different edge levels of detail before run time.

4. The method of claim 3 including looking up the pre-computed inner tessellation values at run time.

5. The method of claim 4 including pre-computing the triangulation of the inner tessellation.

6. The method of claim 1 including using 1-axis inner tessellation factor axis reduction.

7. The method of claim 1 including using a quad as the primitive domain for the tessellation.

8. The method of claim 1 including sorting and grouping patches with the same edge level of detail on separate physical cores.

9. The method of claim 8 including threading and vectorizing.

10. An apparatus comprising:

a hull shader; and

a tessellator coupled to said hull shader to form a tessellation whose tessellation time increase linearly with increasing tessellation level of detail.

11. The apparatus of claim 10 wherein tessellator is a software tessellator.

12. The apparatus of claim 10 wherein said tessellator to pre-compute inner tessellation values for a plurality of different edge levels of detail before run time.

13. The apparatus of claim 12, said tessellator to look up the pre-computed inner tessellation values at run time.

14. The apparatus of claim 13, said tessellator to pre-compute the triangulation of the inner tessellation.

15. The apparatus of claim 10, said tessellator to use 1-axis inner tessellation factor axis reduction.

16. The apparatus of claim 10, said tessellator to use as a primitive domain a quad.

17. The apparatus of claim 10, said tessellator to sort in group patches with the same edge level of detail on separate physical cores of a multi-core processor.

18. The apparatus of claim 17, said tessellator to use threading and vectorizing.

22. The system of claim 10 including a software tessellator.

19. A system comprising:

a multi-core processor including at least two cores, each of said cores including a first and second buffer;

a patch sorter to sort patches for tessellation based on their edge level of detail and to provide the patches having the same level of detail to the same core; and

a tessellator to tessellate said patches by pre-computing the intervals and triangulation for the inner tessellations and applying the pre-computed intervals and triangulations during run time using a look up technique.

20. The system of claim 19 using threading and vectorizing.

21. The system of claim 19, said system to perform tessellations where the tessellation time increases linearly with increasing tessellation level of detail.