GRAPHICS PROCESSOR

• US 20100164971A1
• Filed: 12/28/2009
• Published: 07/01/2010
• Est. Priority Date: 12/29/2008
• Status: Abandoned Application

• Current Assignee: Celio Technology Corp.
• Original Assignee: Celio Technology Corp.
• Inventors: Harris, Joseph Arthur
• Application Number:
  US12/648,156
• Publication Number:
  US 20100164971A1
• Time in Patent Office: Days
• US Class Current: 345/560
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A graphics processor for processing graphics data originating in a host device into rendered graphics data employable in a remote display device. The graphics processor includes a video processor with a reduced instruction-set computer coupled to a configuration register for producing rendered graphics data from the graphics data in a memory storage structure. A first line buffer affords the video processor read-only access to the graphics data in the memory storage structure, and a second line buffer affords the video processor write access to the memory storage structure for rendered graphics data. A method of processing graphics data includes the steps of moving graphics data from the host device into a memory storage structure, transferring the graphics data from the memory storage structure to the video processor, processing the graphics data in the video processor, and writing the rendered graphics data into the memory storage structure.

Claims

1. A graphics processor for processing graphics data housed in a memory storage structure and originating in a host device into rendered graphics data employable in a display device of remote from the host device, the graphics processor comprising:

(a) a video processor capable of producing rendered graphics data from the graphics data in the memory storage structure;

(b) an operational storage medium coupled directly to the video processor;

(c) a first line buffer coupled to the video processor and coupleable to a memory storage structure, the first line buffer being a read-only buffer; and

(d) a second line buffer coupled to the video processor and coupleable to the memory storage structure, the second line buffer being a substantially write-only buffer.

2. A graphics processor as recited in claim 1, wherein the first line buffer is capable of reading across line boundaries in the graphics data in the memory storage structure.

3. A graphics processor as recited in claim 1, wherein the second line buffer includes a limited read-only capability.

4. A graphics processor as recited in claim 3, wherein the second line buffer is incapable of reading across line boundaries in the graphics data in the memory storage structure.

5. A graphics processor as recited in claim 1, further comprising control circuitry for the first line buffer and for the second line buffer, the control circuitry being coupled to the video processor.

6. A graphics processor as recited in claim 1, wherein the operational storage medium comprises a random access memory coupled to the video processor and to the data buffering system.

7. A graphics processor as recited in claim 1, wherein the video processor comprises:

(a) a reduced instruction-set computer coupled to the data buffering system; and

(b) configuration registers coupled to the reduced instruction-set computer.

8. A graphics processor for processing graphics data housed in a memory storage structure and originating in a host device into rendered graphics data employable in a display device remote from the host device, the graphics processor comprising:

(a) a video processor capable of producing rendered graphics data from the graphics data in the memory storage structure, the video processor comprising;

(i) a reduced instruction-set computer; and

(ii) configuration registers coupled to the reduced instruction-set computer;

(b) an operational storage medium coupled directly to the video processor; and

(c) a parallel-channel data buffering system coupled between the video processor and the memory storage structure, the data buffering system affording read-only access by the video processor to the graphics data in the memory storage structure and substantially write-only access to the memory storage structure for the rendered graphics data from the video processor.

9. A graphics processor as recited in claim 8, wherein the reduced instruction-set computer comprises an instruction set consisting of 27 executable instructions.

10. A graphics processor as recited in claim 8, wherein the reduced instruction-set computer comprises an A-register, an X-register, a program counter and a stack pointer.

11. A graphics processor as recited in claim 8, wherein the data buffering system comprises:

(a) a first line buffer coupled to the video processor and coupleable to the memory storage structure, the first line buffer being a read-only buffer; and

(b) a second line buffer coupled to the video processor and coupleable to the memory storage structure, the second line buffer being a substantially write-only buffer.

12. A graphics processor as recited in claim 11, wherein the second line buffer includes a read-only capability.

13. An enhancer for a host device capable of processing graphics data originating in the host device into rendered graphics data employable in a display device remote from the host device, the enhancer comprising:

(a) a memory storage structure for housing the graphics data generated in the host device;

(b) a processor coupled to the memory storage structure and to the host device, the processor comprising;

(i) a reduced instruction-set computer coupled to the data buffering system; and

(ii) configuration registers coupled between the reduced instruction-set computer and the processor;

(c) a video processor coupled directly to the processor, the video processor being capable of producing from the graphics data in the memory storage structure rendered graphics data employable in a display device;

(d) an operational memory storage medium coupled directly to the video processor;

(e) a parallel-channel data buffering system coupled between the video processor and the memory storage structure, the data buffering system affording read-only access by the video processor to the graphics data in the memory storage structure and substantially write-only access to the memory storage structure for the rendered graphics data from the video processor.

14. An enhancer as recited in claim 13, wherein the data buffering system comprises:

(a) a first line buffer coupled between the video processor and the memory storage structure, the first line buffer being a read-only buffer; and

(b) a second line buffer coupled between the video processor and the memory storage structure, the second line buffer being a substantially write-only buffer.

15. An enhancer as recited in claim 14, wherein:

(a) the first line buffer is capable of reading across line boundaries in the graphics data in the memory storage structure; and

(b) the second line buffer is incapable of reading across line boundaries in the graphics data in the memory storage structure.

16. A system for processing graphics data into rendered graphics data, the system comprising:

(a) a host device containing executable code for generating the graphics data;

(b) an enhancer for the host device coupled thereto, the enhancer comprising;

(i) a memory storage structure for housing the graphics data generated in the host device;

(ii) a processor coupled to the memory storage structure and to the host device;

(iii) a video processor coupled directly to the processor, the video processor being capable of producing from the graphics data in the memory storage structure rendered graphics data employable in a display device;

(iv) an operational storage medium coupled directly to the video processor;

(v) a first line buffer coupled between the video processor and the memory storage structure, the first line buffer being a read-only buffer; and

(iv) a second line buffer coupled between the video processor and the memory storage structure, the second line buffer being a substantially write-only buffer.

17. A system as recited in claim 16, wherein the first line buffer is capable of reading across line boundaries in the graphics data in the memory storage structure.

18. A system as recited in claim 16, wherein the second line buffer is incapable of reading across line boundaries in the graphics data in the memory storage structure.

19. A system as recited in claim 16, further comprising a display device remote from the host device and coupled to the enhancer, the display device being capable of exhibiting the rendered graphics data.

20. A system as recited in claim 16, further comprising a keyboard of relatively commodious proportions coupled to the enhancer, affording an operator of the system easier control of the system than the control of the system afforded by the input capability of the host device.

21. A system as recited in claim 16, wherein the host device comprises a device selected from the group of devices comprising a cellular phone, a smart phone, a personal digital assistant, an electronic book, and a personal media player.

22. A method for processing graphics data from a host device, the method comprising the steps of:

(a) moving the graphics data from the host device into a memory storage structure;

(b) transferring the graphics data from the memory storage structure to a video processor;

(c) processing the graphics data in the video processor into rendered graphics data exhibitable by a display device remotely located from the host device; and

(d) writing the rendered graphics data into the memory storage structure.

23. A method as recited in claim 22, wherein the step of transferring comprises the steps of:

(a) reading the graphics data from the memory storage structure into a first buffer; and

(b) communicating the graphics data from the first buffer to the video processor.

24. A method as recited in claim 23, wherein the step of transferring further comprises the steps of:

(a) fetching additional graphics data from the memory storage structure into the first buffer; and

(b) relaying the additional graphics data from the first buffer to the video processor.

25. A method as recited in claim 23, wherein the step of transferring further comprises the steps of:

(a) transcribing destination line graphics data from the memory storage structure into a second buffer; and

(b) delivering the destination line graphics data from the second buffer to the video processor.

26. A method as recited in claim 22, wherein the step of writing comprises the steps of:

(a) storing the rendered graphics data in the second buffer; and

(b) passing the rendered graphics data from the second buffer into the memory storage structure.