SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF NON-VOLATILE MEMORY OPERATIONS

• US 20100174849A1
• Filed: 01/07/2009
• Published: 07/08/2010
• Est. Priority Date: 01/07/2009
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: SiliconSystems, Inc. (Western Digital Corporation)
• Inventors: Walston, Wesley, Diggs, Mark S.
• Granted Patent: US 9,176,859 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 3/061 Improving I/O performance

Abstract

Disclosed herein are systems and methods that recognize and recapture potentially unused processing time in typical page program and block erase operations in non-volatile memory (NVM) devices. In one embodiment, a characterization module within a controller executes a characterization procedure by performing page program and block erase operations on one or more NVM devices in an array and storing execution time data of the operations in a calibration table. The procedure may be executed at start-up and/or periodically so that the time values are reflective of the actual physical condition of the individual NVM devices. A task manager uses the stored time values to estimate the time needed for completing certain memory operations in its task table. Based on the estimated time for completion, the task manager assigns tasks to be executed during page program and/or block erase cycles, so that otherwise unused processing time can be utilized.

Claims

1. A storage subsystem, comprising:

a non-volatile memory array; and

a controller comprising;

a characterization module configured to record, in a calibration table, execution times of memory operations performed on a plurality of memory devices in the non-volatile memory array; and

a task manager that uses the times from the calibration table to select one or more tasks to be executed while the controller is performing a current memory operation, the selected tasks having a total execution time less than the recorded execution time associated with the current memory operation.

2. The storage subsystem of claim 1, wherein the memory operations are memory operations executed during the course of normal usage of the storage subsystem.

3. The storage subsystem of claim 1, wherein the memory operations are calibration operations.

4. The storage subsystem of claim 3, wherein the characterization module is configured to perform calibration operations as triggered by a monitored event.

5. The storage subsystem of claim 4, wherein the monitored event is a temperature change by one or more present threshold values.

6. The storage subsystem of claim 4, wherein the monitored event is an increase in usage of the storage subsystem by a threshold amount.

7. The storage subsystem of claim 4, wherein the monitored event is reaching a threshold amount of power-on time.

8. The storage subsystem of claim 4, wherein the monitored event is reaching a threshold number of power up.

9. The storage subsystem of claim 4, wherein the monitored event is a voltage level change by a threshold amount.

10. The storage subsystem of claim 1, wherein the recorded times comprise execution time data associated with particular blocks of the non-volatile memory array.

11. The storage subsystem of claim 10, wherein the recorded times comprise separate execution time data associated with particular blocks of the non-volatile memory array.

12. The storage subsystem of claim 10, wherein the recorded times are execution time data associated with page programming cycles of particular blocks of the non-volatile memory array.

13. The storage subsystem of claim 10, wherein the recorded times are execution time data associated with block erase cycles of particular blocks of the non-volatile memory array.

14. The storage subsystem of claim 1, wherein the recorded times comprise execution time data associated with different monitored conditions of the non-volatile memory array.

15. A method for optimizing memory operations executed by a controller for a storage subsystem, comprising:

executing a plurality of memory operations on a plurality of memory devices in a storage subsystem;

recording execution times of the plurality of memory operations;

selecting for execution one or more tasks with a total recorded execution time that is less than the recorded execution time of a current memory operation; and

executing the selected tasks while the current memory operation is being executed.

16. The method of claim 15, wherein the memory operations are memory operations executed during the course of normal usage of the storage subsystem.

17. The method of claim 15, wherein the memory operations are calibration operations.

18. The method of claim 15, wherein the current memory operation is a page programming operation.

19. The method of claim 15, wherein the current memory operation is a block erase operation.

20. The method of claim 15, wherein the executing and recoding are performed when triggered by a monitored event.

21. The method of claim 20, wherein the monitored event is a temperature change by one or more present threshold values.

22. The method of claim 20, wherein the monitored event is an increase in usage of the storage subsystem by a threshold amount.

23. The method of claim 20, wherein the monitored event is reaching a threshold amount of power-on time.

24. The method of claim 20, wherein the monitored event is reaching a threshold number of power up.

25. The method of claim 20, wherein the monitored event is a voltage level change by a threshold amount.

26. A computer-readable medium having stored thereon executable code which, when executed by a computer, causes the computer to perform the method of claim 15.

27. A storage subsystem, comprising:

a solid state non-volatile memory array, and

a controller that is operative to write data to, and read data from, the solid state non-volatile memory in response to memory access commands received from a host system, the controller additionally operative to record, for each of a plurality of regions of the non-volatile solid state memory array, execution time data reflective of memory access operation execution times for the respective regions, the controller further operative to use the recorded execution times to select tasks to perform concurrently with particular memory access operations initiated by the host system.