Multipurpose Photodetector Amplifier and Control Methods

• US 20100176275A1
• Filed: 03/31/2009
• Published: 07/15/2010
• Est. Priority Date: 01/15/2009
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Hoffman, Alan W., Vampola, John L.
• Granted Patent: US 8,258,451 B2
• Time in Patent Office: Days
• US Class Current: 250/214.A
• CPC Class Codes: H04N 25/50 Control of the SSIS exposure
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

In certain embodiments, a system is provided for image capture that includes a unit cell that includes a Capacitor TransImpedance Amplifier (CTIA) subcircuit, a Source Follower per Detector (SFD) subcircuit, and a Direct Injection (DI) subcircuit. The unit cell may operate using one of the subcircuits selected in response to a control signal. A column amplifier may be coupled to the unit cell. The column amplifier may be operable to receive an intermediate signal from the unit cell and couple components of the column amplifier corresponding to the selected subcircuit in response to the control signal. The column amplifier may generate an output signal from the intermediate signal using the coupled components of the column amplifier.

Claims

1. A system for image capture, comprising:

a unit cell comprising;

a capacitor transimpedance amplifier (CTIA) subcircuit;

a source follower per detector (SFD) subcircuit; and

a direct injection (DI) subcircuit;

wherein the unit cell operates using one of the CTIA subcircuit, the SFD subcircuit, or the DI subcircuit selected in response to a control signal; and

a column amplifier coupled to the unit cell, the column amplifier operable to;

receive an intermediate signal from the unit cell;

couple components of the column amplifier corresponding to the selected subcircuit in response to the control signal; and

generate an output signal from the intermediate signal using the coupled components of the column amplifier.

2. The system of claim 1, wherein the column amplifier comprises:

a first amplifier;

a current source;

a second amplifier;

a first switch coupled to the input of the first amplifier;

a second switch coupled to the output of the first amplifier;

a third switch coupled to the current source;

a fourth switch coupled to input of the second amplifier; and

a fifth switch coupled to the output of the second amplifier;

wherein the first, third, and fourth switches are coupled to the unit cell; and

wherein the second and fifth switches are coupled to an output node.

3. The system of claim 1, wherein the CTIA subcircuit comprises:

a first transistor;

a second transistor;

a cascode transistor;

a feedback capacitor;

an enable transistor; and

a reset transistor;

wherein the first transistor and cascode transistors are coupled in series, and the second transistor, the feedback capacitor, the reset transistor, the cascode transistor, and the enable transistor are coupled to a common node.

4. The system of claim 3, wherein:

the unit cell is operating in a CTIA capture mode;

the first transistor is biased to maintain the cascode transistor in saturation;

the second transistor is on;

the enable transistor is off; and

the reset transistor provides a current to the cascode and first transistor.

5. The system of claim 3, wherein:

the unit cell is operating in a CTIA read mode;

the first transistor is biased to maintain the cascode transistor in saturation;

the second transistor is on;

the enable transistor is on;

the reset transistor provides a current to the cascode and first transistor; and

an intermediate signal is communicated from the unit cell to the column amplifier.

6. The system of claim 3, wherein:

the unit cell is operating in a CTIA reset mode;

the first transistor is biased to maintain the cascode transistor in saturation;

the second transistor is off;

the enable transistor is off;

the reset transistor provides a current to the cascode and first transistor; and

charge is drained from the unit cell through the second transistor.

7. The system of claim 1, wherein the SFD subcircuit comprises:

a first transistor;

a second transistor;

a cascode transistor;

an enable transistor; and

a reset transistor;

wherein the first transistor is coupled to a second transistor, the first transistor and cascode transistors are coupled in series, and wherein the reset transistor, the cascode transistor, the second transistor and the enable transistor are coupled to a common node.

8. The system of claim 7, wherein:

the unit cell is operating in a SFD capture mode;

the first transistor is on;

the second transistor is off

the cascode transistor is on;

the enable transistor is off; and

the reset transistor is off.

9. The system of claim 7, wherein:

the unit cell is operating in a SFD read mode;

the first transistor is on;

the second transistor is off

the cascode transistor is on;

the enable transistor is on;

the reset transistor is off; and

an intermediate signal is communicated from the unit cell to the column amplifier.

10. The system of claim 7, wherein:

the unit cell is operating in a SFD reset mode;

the first transistor is on;

the cascode transistor is on;

the second transistor is on;

the enable transistor is off;

the reset transistor is on; and

charge is drained from the unit cell through the second transistor and the reset transistor.

11. The system of claim 1, wherein the DI subcircuit comprises:

a transistor;

an integration capacitor;

an enable transistor; and

a reset transistor;

wherein the transistor, the integration capacitor, the enable transistor, and the reset transistor are coupled to a common node.

12. The system of claim 11, wherein:

the unit cell is operating in a DI capture mode;

the transistor is on;

the reset transistor is off;

the enable transistor is off; and

charge is accumulated at the integration capacitor.

13. The system of claim 11, wherein:

the unit cell is operating in a DI read mode;

the transistor is on;

the reset transistor is off;

the enable transistor is off; and

an intermediate signal is communicated from the unit cell to the column amplifier.

14. The system of claim 11, wherein:

the unit cell is operating in a DI reset mode;

the transistor is on;

the reset transistor is on;

the enable transistor is off; and

charge is drained from the unit cell through the reset transistor.

15. A method for image capture, comprising:

receiving a control signal at circuitry controlling a unit cell;

determining a mode of operation of the unit cell based on the control signal, the mode of operation comprising one of a capacitor transimpedance amplifier, source follower per detector, or direct injection;

applying voltages to components of the unit cell based on the mode of operation determined by the control signal;

coupling particular circuit components of a column amplifier to the unit cell in response to the control signal; and

generating an output signal from an intermediate signal using the coupled components of the column amplifier.

16. The method of claim 15, further comprising:

controlling switches at a column amplifier coupled to the unit cell, the switches being connected or disconnected based on the mode of operation determined by the control signal.

17. A system for image capture, comprising:

a first unit cell operable to;

accumulate charge in proportion to an intensity of light received at the first unit cell; and

send a first intermediate signal;

a second unit cell operable to;

accumulate charge in proportion to an intensity of light received at the second unit cell; and

send a second intermediate signal; and

the first and second unit cells coupled to a column amplifier, the column amplifier operable to;

receive the first intermediate signal and generate a first output signal; and

receive the second intermediate signal and generate a second output signal.

18. The system of claim 17, wherein the first and second unit cells are part of an array of unit cells and the unit cells in a column of the array of unit cells are each coupled to the column amplifier.

19. The system of claim 17, further comprising:

circuitry coupled to the first unit cell operable to;

receive a control signal;

cause voltages to be applied to components of the first unit cell based on the control signal.

20. The system of claim 19, wherein the control signal is a first control signal and further comprising:

circuitry coupled to the second unit cell operable to;

receive a second control signal different from the first control signal;

cause voltages to be applied to components of the second unit cell based on the second control signal.