Semiconductor Device

• US 20100181606A1
• Filed: 06/17/2008
• Published: 07/22/2010
• Est. Priority Date: 06/19/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Takaishi, Masaru
• Granted Patent: US 8,816,419 B2
• Time in Patent Office: Days
• US Class Current: 257/300
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

Provided is a semiconductor device having a high switching speed. A semiconductor device (20) is provided with an n-type epitaxial layer (2) having a plurality of trenches (3) arranged at prescribed intervals (b); an embedded electrode (5) formed on an inner surface of the trench (3) through a silicon oxide film (4) to embed each trench (3); and a metal layer (7), which is capacitively coupled with the embedded electrode (5) by being arranged above the embedded electrode (5) through a silicon oxide film (6). In the semiconductor device (20), a region between the adjacent trenches (3) operates as a channel (current path)(11). A current flowing in the channel (11) is interrupted by covering the region with a depletion layer formed at the periphery of the trenches (3), and the current is permitted to flow through the channel (11) by eliminating the depletion layer at the periphery of the trenches (3).

Claims

1. A semiconductor device comprising:

a semiconductor layer of one conductivity type having a plurality of trenches arranged at a predetermined interval from one another;

a plurality of buried electrodes buried in the plurality of trenches respectively; and

a conductor layer inside at least one of the plurality of trenches, the conductor layer being arranged above the buried electrodes with a first insulation film interposed in between so as to be capacitively coupled to the buried electrodes.

2. The semiconductor device of claim 1, wherein the semiconductor layer is configured such that regions between mutually adjacent ones of the trenches serve as current passages respectively,

the semiconductor device arranged to operate such that, when depletion layers are formed around the plurality of trenches, the regions between the mutually adjacent ones of the trenches are thereby stopped and the current passages are cut off, and when at least part of the depletion layers formed around the trenches disappears, the current passages are opened.

3. The semiconductor device of claim 1, wherein

the conductor layer is formed inside each of the plurality of trenches and is capacitively coupled to the buried electrodes respectively.

4. The semiconductor device of claim 1, wherein

a second insulation film is on a top face of the conductor layer, and

the second insulation film is inside the trenches such that a top face of the second insulation film is flush with a top face of the semiconductor layer.

5. The semiconductor device of claim 1, wherein

a predetermined one of the plurality of buried electrodes is on an interior surface of the trenches with a third insulation film interposed in between, and

a thickness of the first insulation film is equal to or larger than a thickness of the third insulation film.

6. The semiconductor device of claim 1, wherein a width of the conductor layer in a direction of arrangement of the trenches is smaller than a width of the buried electrodes.

7. The semiconductor device of claim 1, wherein the conductor layer is formed of a metal material.

8. The semiconductor device of claim 7, wherein the conductor layer comprises at least one metal material selected from the group of W, Ti, and TiN.

9. The semiconductor device of claim 1, wherein the plurality of trenches are each in an elongate shape so as to extend parallel to one another in a direction parallel to a top face of the semiconductor layer and perpendicular to a direction of arrangement of the trenches.

10. The semiconductor device of claim 2, wherein the semiconductor device is arranged to operate such that:

the current passages are cut off as a result of all the depletion layers formed around the plurality of trenches respectively stopping the regions between the mutually adjacent ones of the trenches, and

the current passages are opened as a result of all the depletion layers formed around the plurality of trenches respectively disappearing.

11. The semiconductor device of claim 2, wherein the semiconductor device is arranged to operate such that:

the plurality of buried electrodes comprise first buried electrodes and second buried electrodes to which separate voltages are applied,

the current passages are cut off as a result of the depletion layers formed around, of the plurality of trenches, all the trenches stopping the regions between the mutually adjacent ones of the trenches, and

the current passages are opened as a result of the depletion layers formed around, of the plurality of trenches, the trenches having the first buried electrodes buried therein disappearing.

12. The semiconductor device of claim 11, wherein the second buried electrodes make Schottky contact with the semiconductor layer inside the trenches.

13. The semiconductor device of claim 2, further comprising:

diffusion regions of an opposite conductivity type formed respectively in the regions between the mutually adjacent ones of the trenches in the semiconductor layer and arranged at a predetermined interval from the trenches, wherein the semiconductor device is arranged to operate such that;

the current passages are cut off as a result of the depletion layers formed around the trenches and the diffusion regions respectively stopping the regions between the mutually adjacent ones of the trenches, and

the current passages are opened as a result of the depletion layers formed around the trenches respectively disappearing.

14. A semiconductor device comprising:

a semiconductor layer of one conductivity type having a plurality of trenches arranged at a predetermined interval from one another;

a plurality of buried electrodes buried inside the plurality of trenches; and

a capacitor in a predetermined region on the semiconductor layer with an insulation/separation layer interposed in between, the capacitor at least including a fourth insulation film, a first electrode, and a second electrode, the fourth insulation film being disposed laid between the first and second electrodes, wherein

the capacitor and the buried electrodes are electrically connected together, and, during operation, a voltage is applied to the buried electrodes via the capacitor.

15. The semiconductor device of claim 14, wherein

the semiconductor layer is configured such that regions between mutually adjacent ones of the trenches serve as current passages respectively, the semiconductor device arranged to operate such that:

when depletion layers are formed around the plurality of trenches, the regions between the mutually adjacent ones of the trenches are thereby stopped and the current passages are cut off, and

when at least part of the depletion layers formed around the trenches disappear, the current passages are opened.

16. The semiconductor device of claim 14, wherein the capacitor is in a region in a peripheral part on the semiconductor layer.

17. The semiconductor device of claim 14, wherein the first and second electrodes comprise conductive polysilicon.

18. The semiconductor device of claim 14, further comprising:

an interlayer insulation film on a top face of the buried electrodes, and

the interlayer insulation film is inside the trenches such that a top face of the interlayer insulation film is flush with a top face of the semiconductor layer.

19. The semiconductor device of claim 14, wherein

a predetermined one of the plurality of buried electrodes is on an interior surface of the trenches with a fifth insulation film interposed in between, and

a thickness of the fourth insulation film is equal to or larger than a thickness of the fifth insulation film.

20. The semiconductor device of claim 14, wherein the plurality of trenches are each in an elongate shape so as to extend parallel to one another in a direction parallel to a top face of the semiconductor layer and crossing a direction of arrangement of the trenches.

21. The semiconductor device of claim 15, wherein the semiconductor device is arranged to operate such that:

the current passages are cut off as a result of all the depletion layers formed around the plurality of trenches respectively stopping the regions between the mutually adjacent ones of the trenches, and

the current passages are opened as a result of all the depletion layers formed around the plurality of trenches respectively disappearing.

22. The semiconductor device of claim 15, wherein

the plurality of buried electrodes comprise first buried electrodes and second buried electrodes to which separate voltages are applied,

the current passages are cut off as a result of the depletion layers formed around, of the plurality of trenches, all the trenches stopping the regions between the mutually adjacent ones of the trenches, and

the current passages are opened as a result of the depletion layers formed around, of the plurality of trenches, the trenches having the first buried electrodes buried therein disappearing.

23. The semiconductor device of claim 22, wherein the second buried electrodes make Schottky contact with the semiconductor layer inside the trenches.

24. The semiconductor device of claim 15 wherein

diffusion regions of an opposite conductivity type are respectively in the regions between the mutually adjacent ones of the trenches in the semiconductor layer and arranged at a predetermined interval from the trenches, wherein the semiconductor device is arranged to operate such that:

the current passages are cut off as a result of the depletion layers formed around the trenches and the diffusion regions respectively stopping the regions between the mutually adjacent ones of the trenches, and

the current passages are opened as a result of the depletion layers formed around the trenches respectively disappearing.