Enhanced Error Detection in Multilink Serdes Channels

• US 20100185919A1
• Filed: 03/03/2009
• Published: 07/22/2010
• Est. Priority Date: 01/21/2009
• Status: Active Grant

• Current Assignee: Cisco Systems, Inc.
• Original Assignee: Cisco Systems, Inc.
• Inventors: Walker, David S., Lawson, Matthew Todd
• Granted Patent: US 8,332,721 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 2001/0094 Bus

Abstract

A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.

Claims

1. A method comprising:

receiving an encoded frame via a serial communication link;

calculating a first cyclic redundancy check (CRC) for the encoded frame;

comparing the generated first CRC with a second CRC, wherein the second CRC is included in the encoded frame;

if the first and second CRCs match, decoding the encoded frame; and

if the first and second CRCs do not match, discarding the encoded frame.

2. The method of claim 1 further comprising:

forming a plurality of segments, wherein

a first segment of the plurality of segments comprises a portion of the received encoded frame, wherein the portion is less than all of the encoded frame, and

each segment of the plurality of segments comprises respective frame header information and respective frame payload information.

3. The method of claim 2, wherein

the first segment comprises 24 bits of frame payload information and 2 bits of frame header information.

4. The method of claim 2, wherein

the first segment comprises one bit of the second CRC.

5. The method of claim 2, further comprising

extracting frame payload information from the first segment to produce extracted frame payload information;

and

forming a transport layer packet, wherein

the transport layer packet includes the extracted frame payload information, and

the transport layer packet includes a third CRC.

6. The method of claim 2, further comprising:

determining whether frame payload information from the first segment comprises a portion of one or more transport layer packets, wherein the determining is based on the value of a virtual delimiter included in the encoded frame.

7. The method of claim 1, wherein the second CRC is calculated using the same algorithm that was used to calculate the first CRC.

8. The method of claim 1, further comprising

descrambling the encoded frame.

9. The method of claim 8, further comprising

initializing a descrambler with an initial value that was used to initialize a scrambler, wherein the scrambler scrambled the encoded frame.

10. An apparatus comprising:

a first circuit configured to

receive an encoded frame via a serial communication link;

calculate a first cyclic redundancy check (CRC) for the encoded frame;

compare the generated first CRC with a second CRC, wherein the second CRC is included in the encoded frame;

decode the encoded frame if the first CRC and second CRC match; and

discard the encoded frame if the first CRC and second CRC do not match.

11. The apparatus of claim 10 further comprising:

a second circuit configured to

form a plurality of segments, wherein

a first segment of the plurality of segments comprises a portion of the received encoded frame, wherein the portion is less than all of the encoded frame, and

each segment of the plurality of segments comprises respective frame header information and respective frame payload information.

12. The apparatus of claim 11, wherein

the first segment comprises 24 bits of frame payload information and 2 bits of frame header information.

13. The apparatus of claim 11, wherein

the first segment comprises one bit of the second CRC.

14. The apparatus of claim 11, further comprising

a third circuit configured to

extract frame payload information from the first segment to produce extracted frame payload information;

and

form a transport layer packet, wherein

the transport layer packet includes the extracted frame payload information, and

the transport layer packet includes a third CRC.

15. The apparatus of claim 11, further comprising:

determining whether frame payload information from the first segment comprises a portion of one or more transport layer packets, wherein the determining is based on the value of a virtual delimiter included in the encoded frame.

16. The apparatus of claim 10 wherein the second CRC is calculated using the same algorithm that was used to calculate the first CRC.

17. The apparatus of claim 10, further comprising

a fourth circuit configured to descramble the encoded frame.

18. The apparatus of claim 17, further comprising

a fifth circuit configured to

initialize a descrambler with an initial value that was used to initialize a scrambler, wherein the scrambler scrambled the encoded frame.

19. An apparatus comprising:

a first means for

receiving an encoded frame via a serial communication link;

calculating a first cyclic redundancy check (CRC) for the encoded frame;

comparing the generated first CRC with a second CRC, wherein the second CRC is included in the encoded frame;

if the first and second CRCs match, decoding the encoded frame; and

if the first and second CRCs do not match, discarding the encoded frame.