TAMPER-RESISTANT SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THEREOF

• US 20100187527A1
• Filed: 07/29/2008
• Published: 07/29/2010
• Est. Priority Date: 08/02/2007
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van Geloven, Johannes A. J., Tuyles, Pim T., Verhaegh, Nynke, Wolters, Robertus A. M.
• Granted Patent: US 8,143,705 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The invention relates to a tamper-resistant semiconductor device comprising a substrate (5) comprising an electronic circuit arranged on a first side thereof. An electrically-conductive protection layer (50, 50a, 50b) is arranged on a second side of the substrate (5) opposite to the first side. At least three through-substrate electrically-conductive connections (45) extend from the first side of the substrate (5) into the substrate (5) and in electrical contact with the electrically-conductive protection layer (50, 50a, 50b) on the second side of the substrate (5). A security circuit is arranged on the first side connected to the through-substrate electrically-conductive connections (45) and is arranged for measuring at least two resistance values (R12, R23, R34, R14, R13, R24) of the electrically-conductive protection layer (50, 50a, 50b) through the through-substrate electrically-conductive connections (45). The security circuit is further arranged for comparing the measured resistance values (R12, R23, R34, R14, R13, R24) with reference resistance values.

Claims

1. A tamper-resistant semiconductor device comprising:

a semiconductor substrate comprising an electronic circuit arranged on a first side thereof;

the semiconductor device having an electrically-conductive productive protection layer arranged on a second side of the semiconductor substrate opposite to the first side;

at least three through-substrate electrically-conductive connections extending from the first side of the semiconductor substrate into the semiconductor substrate and in electrical contact with the electrically-conductive protection layer on the second side of the substrate;

a security circuit being arranged on the first side connected to the through-substrate electrically-conductive connections and being arranged

i) for measuring at least two resistance values of the electrically-conductive protection layer through the through-substrate electrically-conductive connections to provide a security code, and

ii) for comparing the security code with a reference code.

2. Tamper-resistant semiconductor device as claimed in claim 1, wherein the semiconductor substrate comprises a Silicon-on-Insulator substrate (an SOI-substrate), the SOI-substrate comprising a semiconductor substrate layer, a buried-oxide layer provided on the substrate layer, and an active layer provided on the buried-oxide layer, the active layer being located at the first side of the substrate and the semiconductor substrate layer being located at the second side of the semiconductor substrate, the electronic circuit being provided in the active layer, wherein the through-substrate connections extend from the first side through the active layer and the buried-oxide layer to the semiconductor substrate layer, and wherein the electrically-conductive protection layer, is provided on the semiconductor substrate layer at the second side of the semiconductor substrate.

3. Tamper-resistant semiconductor device as claimed in claim 1, wherein the semiconductor substrate is mounted at its second side on an electrically-conductive semiconductor substrate carrier via an electrically-conductive adhesive layer, wherein the electrically-conductive semiconductor substrate carrier and the electrically-conductive adhesive layer together form the electrically-conductive protection layer.

4. Tamper-resistant semiconductor device as claimed in claim 1, wherein the electrically-conductive protection layer and the through-substrate connections form a region covering a part of the second side of the semiconductor substrate.

6. Tamper-resistant semiconductor device as claimed claim 1, wherein the electrically-conductive protection layer fully covers the second side of the substrate.

7. Tamper-resistant semiconductor device as claimed in claim 1, wherein the number of through-substrate connections equals n, n≧

3, and the number of resistance values measured between pairs of the through-substrate connections equals Z, wherein Z complies with the following equation;

2<

Z≦

(n!/((n−

2)!*2!).

8. Tamper-resistant semiconductor device as claimed in claim 1, wherein the security circuit comprises a circuit selected from the group comprising:

a two-point resistance-measurement circuit, and

a four-point resistance-measurement circuit.

9. Tamper-resistant semiconductor device as claimed in claim 1, wherein neighboring first and a second through-substrate connections are mutually located at a first distance, while neighboring first and third through-substrate connections are located at a second distance unequal to the first distance.

10. Tamper-resistant semiconductor device as claimed in claim 9, wherein a further pair of neighboring through-substrate connections is mutually located at the first distance and the circuit is arranged for use of the further pair as a reference to the pair of the first and second through-substrate connections.

11. Tamper-resistant semiconductor device as claimed in claim 1, wherein the security circuit further comprises a security element at a first side of the semiconductor substrate.

12. Tamper-resistant semiconductor device as claimed claim 1, wherein the electrically-conductive protection layer comprises a composition or material which provides for a pseudo-random or fully-random variable spatial conductivity.

13. Tamper-resistant semiconductor device as claimed in claim 9, wherein the electrically-conductive protection layer comprises a mixture of tin (Sn) and aluminum (Al).

14. Tamper-resistant semiconductor device as claimed in claim 1, where the semiconductor device further comprises at least one light-emitting device and at least one light-sensing device provided on the first side of the semiconductor device, wherein the light-emitting device is arranged to emit light, including a wavelength range for which the substrate is transparent, into the semiconductor substrate towards the second side;

and wherein the light-sensing device is arranged to sense at least a fraction of the emitted light following passage through the substrate and reflection at the second side, and configured to output a signal indicative of a reflecting state of the second side, thereby enabling detection of an attempt to tamper with the second side of the semiconductor device.

16. Method of manufacturing a semiconductor device as claimed in claim 1, the method comprising steps of:

providing the semiconductor substrate having the first side and the second side opposite to the first side;

providing the electronic circuit on the first side of the semiconductor substrate;

providing the at least three through-substrate electrically-conductive connections in the semiconductor substrate, the connections extending from the first side of the substrate to the second side of the substrate, and

providing the security circuit on the first side, and connecting the circuit to the through-substrate electrically-conductive connections, the security circuit being arranged

i) for measuring at least two resistance values of the electrically-conductive protection layer through the through-substrate electrically-conductive connections, and

ii) for comparing the measured resistance values with reference resistance values

providing the electrically-conductive protection layer on the second side of the substrate.

17. Method of manufacturing a semiconductor device as claimed in claim 1, the method comprising steps of:

providing a Silicon-on-Insulator semiconductor substrate (an SOI-semiconductor substrate), the SOI-semiconductor substrate comprising a semiconductor substrate layer, a buried-oxide layer provided on the substrate layer, and an active layer provided on the buried-oxide layer, the active layer being located at the first side of the semiconductor substrate and the semiconductor substrate layer being located at the second side of the semiconductor substrate;

providing the electronic circuit on the first side of the substrate in the active layer;

providing the at least three through-substrate electrically-conductive connections in the semiconductor substrate, the connections extending from the first side of the substrate to the semiconductor substrate layer, and

providing the security circuit on the first side, and connecting the circuit to the through-substrate electrically-conductive connections, the security circuit being arranged

i) for measuring at least two resistance values of the electrically-conductive protection layer through the through-substrate electrically-conductive connections, and

ii) for comparing the measured resistance values with reference resistance values;

providing the electrically-conductive protection layer on the second side of the substrate.

18. A method of authenticating the device of claim 1, comprising:

i) measuring at least two resistance values of the electrically-conductive protection layer through the through-substrate electrically-conductive connections to provide a security code, and

ii) comparing the security code with a reference code.

19. The method as claimed in claim 18, wherein the measuring involves a relative measurement of resistance values.

5. Tamper-resistant semiconductor device as claimed in claim 5, wherein the protection layer is patterned to form said region, and through-substrate connections designed for signal transmission or grounding, are present outside the region.

15. An identification article comprising a tamper-resistant semiconductor device the tamper-resistant semiconductor device comprising:

a semiconductor substrate comprising an electronic circuit arranged on a first side thereof;

the semiconductor device having an electrically-conductive productive protection layer arranged on a second side of the semiconductor substrate opposite to the first side;

at least three through-substrate electrically-conductive connections extending from the first side of the semiconductor substrate into the semiconductor substrate and in electrical contact with the electrically-conductive protection layer on the second side of the substrate;

a security circuit being arranged on the first side connected to the through-substrate electrically-conductive connections and being arranged

i) for measuring at least two resistance values of the electrically-conductive protection layer through the through-substrate electrically-conductive connections to provide a security code, and

ii) for comparing the security code with a reference code.

20. A method of authenticating the article of claim 15, comprising the steps of:

i) measuring at least two resistance values of the electrically-conductive protection layer through the through-substrate electrically-conductive connections to provide a security code, and

ii) comparing the security code with a reference code.

21. The method of claim 20, wherein the measuring involves a relative measurement of resistance values.