THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

• US 20100190334A1
• Filed: 03/24/2010
• Published: 07/29/2010
• Est. Priority Date: 06/24/2003
• Status: Abandoned Application

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Application Number:
  US12/731,087
• Publication Number:
  US 20100190334A1
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor circuit structure includes a support substrate which carries an interconnect region and electronic circuitry. The semiconductor circuit structure includes a device substrate coupled to the interconnect region through a conductive bonding layer. The device substrate includes a planarized surface which faces the conductive bonding layer. The device substrate can carry laterally oriented semiconductor devices which are connected to the electronic circuitry carried by the support substrate. The device substrate can be processed to form vertically oriented semiconductor devices which are connected, through the interconnect region and conductive bonding layer, to the electronic circuitry carried by the support substrate.

Claims

1. A method, comprising:

providing a first substrate which carries a circuit and interconnect region; and

coupling a second substrate to the interconnect region through a conductive bonding layer, wherein the second substrate includes first and second portions and a detach layer.

2. The method of claim 1, further including planarizing an exposed surface of the interconnect region.

3. The method of claim 1, wherein the coupling step includes forming the conductive bonding layer proximate to an exposed surface of the interconnect region.

4. The method of claim 1, further including removing the first portion of the second substrate so the first portion is coupled to the interconnect region through the conductive bonding layer.

5. The method of claim 4, further including planarizing an exposed surface of the second portion of the second substrate.

6. The method of claim 4, further including forming a circuit carried by the second portion of the second substrate.

7. The method of claim 6, further including forming an interconnect region carried by the second portion of the second substrate.

8. The method of claim 5, further including forming a circuit proximate to the planarized surface.

9. The method of claim 8, further including forming an interconnect region proximate to the planarized surface.

10. The method of claim 1, further including planarizing an exposed surface of the second portion of the second substrate.

11. The method of claim 10, wherein the coupling step includes forming a bonding interface proximate to the planarized surface.

12. The method of claim 1, further including removing a portion of the conductive contact region.

13. The method of claim 12, further including forming a dielectric material region in the space occupied by the portion of the conductive contact region that was removed.

14. The method of claim 12, further including forming a via which connects the first and second interconnect regions together.

15. The method of claim 14, wherein the via extends through the space occupied by the portion of the conductive contact region that was removed.

16. The method of claim 1, wherein the second portion includes a stack of semiconductor layers.

17. The method of claim 1, wherein the second portion includes a stack of crystalline semiconductor layers.

18. The method of claim 1, wherein the second portion includes a stack of single crystalline semiconductor layers.

19. The method of claim 1, wherein the second portion includes a stack of blanket layers of semiconductor material.