Systems and Methods for Synchronous, Retimed Analog to Digital Conversion

• US 20100194616A1
• Filed: 06/06/2008
• Published: 08/05/2010
• Est. Priority Date: 06/06/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Chmelar, Erik, Ito, Choshu, Loh, William
• Granted Patent: US 7,956,790 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/361 having a separate comparator and reference value for each quantisation level, i.e. full flash converter type

Abstract

Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.

Claims

1. A retimed analog to digital converter circuit, the circuit comprising:

a first set of sub-level interleaves, wherein the first set of sub-level interleaves includes;

a first sub-level interleave, wherein the first sub-level interleave includes a first set of comparators synchronized to a first clock phase;

a second sub-level interleave, wherein the second sub-level interleave includes a second set of comparators synchronized to a second clock phase;

a second set of sub-level interleaves, wherein the second set of sub-level interleaves includes;

a third sub-level interleave, wherein the third sub-level interleave includes a third set of comparators synchronized to a third clock phase;

a fourth sub-level interleave, wherein the fourth sub-level interleave includes a fourth set of comparators synchronized to a fourth clock phase; and

a global interleave, wherein the global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and wherein the global interleave selects one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves.

2. The circuit of claim 1, wherein an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase.

3. The circuit of claim 2, wherein an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.

4. The circuit of claim 3, wherein the output from the second set of sub-level interleaves is the output of the fourth sub-level interleave synchronized to the first clock phase, and wherein the output from the first set of sub-level interleaves is the output of the second sub-level interleave synchronized to the third clock phase.

5. The circuit of claim 1, wherein the circuit further comprises a number of reference voltages, and wherein each of the number of reference voltages is provided to a respective comparator in each of the first set of comparators, the second set of comparators, the third set of comparators and the fourth set of comparators.

6. The circuit of claim 5, wherein the reference voltages are generated by respective digital to analog converters each receiving a different programmable digital value.

7. The circuit of claim 6, wherein the programmable digital values are maintained in a lookup table.

8. The circuit of claim 1, wherein the outputs from the first set of comparators are provided to a register that is clocked using the third clock phase, and wherein one of the outputs from the register is selected by a multiplexer based at least in part on the output from the second set of sub-level interleaves.

9. The circuit of claim 8, wherein the multiplexer is a first multiplexer, wherein the register is a first register, wherein the outputs from the second set of comparators are provided to a second register that is clocked using the fourth clock phase, and wherein one of the outputs from the second register is selected by a second multiplexer based at least in part on the output from the first multiplexer.

10. The circuit of claim 1, wherein the outputs from the third set of comparators are provided to a register that is clocked using the first clock phase, and wherein one of the outputs from the register is selected by a multiplexer based at least in part on the output from the first set of sub-level interleaves.

11. The circuit of claim 10, wherein the multiplexer is a first multiplexer, wherein the register is a first register, wherein the outputs from the fourth set of comparators are provided to a second register that is clocked using the second clock phase, and wherein one of the outputs from the second register is selected by a second multiplexer based at least in part on the output from the first multiplexer.

12. A method for analog to digital conversion, the method comprising:

performing a first set of analog to digital conversions using a first set of comparators;

performing a second set of analog to digital conversions using a second set of comparators;

performing a third set of analog to digital conversions using a third set of comparators;

performing a fourth set of analog to digital conversions using a fourth set of comparators;

selecting a result from the first set of analog to digital conversions based at least in part on a first registered result to provide a first selected result;

selecting a result from the second set of analog to digital conversions based at least in part on the first selected result to provide a second selected result;

selecting a result from the third set of analog to digital conversions based at least in part on the second registered result to provide a third selected result; and

selecting a result from the fourth set of analog to digital conversions based at least in part on the third selected result to provide a fourth selected result;

registering the fourth selected result to provide the first registered result; and

registering the second selected result to provide the second registered result.

13. The method of claim 12, wherein performing the first set of analog to digital conversions is synchronized to a first clock phase, wherein performing the second set of analog to digital conversions is synchronized to a second clock phase, wherein performing the third set of analog to digital conversions is synchronized to a third clock phase, and wherein performing the fourth set of analog to digital conversions is synchronized to a fourth clock phase.

14. The method of claim 12, wherein registering the fourth selected result is synchronized to the first clock phase, and wherein registering the second selected result is synchronized to the third clock phase.

15. A communication system, the system comprising:

a receiver including a retimed analog to digital converter, wherein the retimed analog to digital converter includes;

a first set of sub-level interleaves, wherein the first set of sub-level interleaves includes;

a first sub-level interleave, wherein the first sub-level interleave includes a first set of comparators synchronized to a first clock phase;

a second sub-level interleave, wherein the second sub-level interleave includes a second set of comparators synchronized to a second clock phase;

a second set of sub-level interleaves, wherein the second set of sub-level interleaves includes;

a third sub-level interleave, wherein the first sub-level interleave includes a third set of comparators synchronized to a third clock phase;

a fourth sub-level interleave, wherein the fourth sub-level interleave includes a fourth set of comparators synchronized to a fourth clock phase; and

a global interleave, wherein the global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and wherein the global interleave selects one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves.

16. The system of claim 15, wherein the system further includes a transmitter and a medium, and wherein information is provided from the transmitter to the receiver via the medium.

17. The system of claim 16, wherein the system is a storage system, and wherein the medium is a storage medium.

18. The system of claim 16, wherein the system is a wireless communication system, and wherein the medium is a wireless communication medium.

19. The system of claim 15, wherein the outputs from the first set of comparators are provided to a first register that is clocked using the third clock phase, wherein one of the outputs from the first register is selected by a first multiplexer based at least in part on the output from the second set of sub-level interleaves, wherein the output from the first multiplexer is provided to a third register that is clocked using the third clock phase, wherein the outputs from the second set of comparators are provided to a second register that is clocked using the fourth clock phase, wherein one of the outputs from the second register is selected by a second multiplexer based at least in part on the output from the first multiplexer, and wherein the output from the second multiplexer is provided to a fourth register that is clocked using the third clock phase.

20. The system of claim 15, wherein the outputs from the third set of comparators are provided to a first register that is clocked using the first clock phase, wherein one of the outputs from the first register is selected by a first multiplexer based at least in part on the output from the first set of sub-level interleaves, wherein the output from the first multiplexer is provided to a third register that is clocked using the first clock phase, wherein the outputs from the second set of comparators are provided to a second register that is clocked using the second clock phase, wherein one of the outputs from the second register is selected by a second multiplexer based at least in part on the output from the first multiplexer, and wherein the output from the second multiplexer is provided to a fourth register that is clocked using the first clock phase.