NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20100207190A1
• Filed: 02/12/2010
• Published: 08/19/2010
• Est. Priority Date: 02/16/2009
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Komori, Yosuke, Fukuzumi, Yoshiaki, Kito, Masaru, Aochi, Hideaki, Kidoh, Masaru, Tanaka, Hiroyasu, Ishiduki, Megumi, KATSUMATA, Ryota
• Granted Patent: US 8,274,108 B2
• Time in Patent Office: Days
• US Class Current: 257/319
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction;

a plurality of selection gate electrodes provided on the stacked body and aligned in the first direction;

a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes and the selection gate electrodes;

a plurality of source lines aligned in the first direction and connected to upper end portions of some of the semiconductor pillars;

a plurality of bit lines aligned in the second direction and connected to upper end portions of a remainder of the semiconductor pillars;

a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to the source line, an upper end portion of the one other of the semiconductor pillars being connected to the bit line;

a charge storage layer provided between one of the control gate electrode and one of the semiconductor pillar; and

a gate insulating film provided between one of the selection gate electrode and one of the semiconductor pillar,

at least some of the control gate electrodes being pierced by two of the semiconductor pillars adjacent to each other in the second direction, two of the semiconductor pillars being connected to each other by the connection member and provided to pierce mutually different control gate electrodes.

2. The device according to claim 1, wherein

the control gate electrodes are organized into a plurality of blocks set along the second direction,

the control gate electrodes of each of the blocks are further organized into two groups,

the control gate electrodes of one group are alternately arranged along the second direction with the control gate electrodes of another group in each of the blocks,

the control gate electrodes of each of the groups have a common connection for the group, and

a lower end portion of the semiconductor pillar disposed at an end portion in the second-direction of each of the blocks is not connected to the connection member.

3. The device according to claim 2, further comprising:

a substrate; and

a back gate provided between the substrate and the stacked body,

the connection member being disposed in an interior of the back gate,

the back gate not being provided in a region directly below a semiconductor pillar not connected to the connection member.

4. The device according to claim 2, wherein the electrode films of each of the blocks are subdivided into a pair of mutually meshed comb-shaped patterns.

5. The device according to claim 2, wherein a control gate electrode is disposed between the two adjacent blocks and connected to none of the control gate electrodes of the one group and the control gate electrodes of the another group of each of the two blocks.

6. The device according to claim 5, wherein a configuration of the control gate electrode connected to none is a line configuration aligned in the first direction.

7. The device according to claim 5, wherein the control gate electrode connected to none is in a floating state.

8. The device according to claim 5, wherein the control gate electrodes of the one group, the control gate electrode connected to none, and the control gate electrodes of the another group are arranged with uniform spacing along the second direction.

9. The device according to claim 5, wherein

the control gate electrode connected to none is pierced by two of the semiconductor pillars, the two of the semiconductor pillars being adjacent in the second direction and connected to a common one of the source lines, and

another two of the semiconductor pillars on each adjacent side in the second direction of the two of the semiconductor pillars piercing the control gate electrode connected to none are connected to one of the bit lines.

10. The device according to claim 5, wherein

the control gate electrode connected to none is pierced by two of the semiconductor pillars, the two of the semiconductor pillars being adjacent in the second direction and connected to a common one of the source lines, and

as viewed from the two of the semiconductor pillars, another two of the semiconductor pillars disposed on one side adjacent in the second direction are connected to one of the bit lines and still another two of the semiconductor pillars disposed on another side adjacent in the second direction are connected to one of the source lines.

11. The device according to claim 5, wherein

the control gate electrode connected to none is pierced by one series of dummy semiconductor pillars arranged along the first direction,

the dummy semiconductor pillars are connected to the connection member connected to two of the semiconductor pillars disposed on each side of the dummy semiconductor pillars, and

the two of the semiconductor pillars are connected to the source lines.

12. The device according to claim 11, wherein the dummy semiconductor pillars are connected to one of the source lines connected to one of the two of the semiconductor pillars.

13. The device according to claim 12, wherein a width of the one of the source lines connected to the dummy semiconductor pillars is wider than a width of another one of the source lines.

14. The device according to claim 1, further comprising:

a substrate; and

a back gate provided between the substrate and the stacked body,

the connection member being disposed in an interior of the back gate.

15. A method for manufacturing a nonvolatile semiconductor memory device, comprising:

forming a conducting film on a substrate;

making a plurality of recesses in an upper face of the conducting film, the recesses being arranged in a matrix configuration along a first direction and a second direction intersecting the first direction;

filling sacrificial members into the recesses;

forming a stacked body on the conducting film, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films;

making through-holes in the stacked body, the through-holes being aligned in a stacking direction of the stacked body and provided in a matrix configuration along the first direction and the second direction, two of the through-holes adjacent in the second direction reaching each of the sacrificial members;

performing etching via the through-holes to remove the sacrificial members;

forming a charge storage layer on inner faces of the through-holes and the recesses;

filling a semiconductor material into interiors of the through-holes and the recesses to form a connection member in the recesses and semiconductor pillars in the through-holes;

making a trench in the stacked body to divide the electrode films into a plurality of control gate electrodes aligned in the first direction, the trench being aligned in the first direction to link regions between two of the semiconductor pillars connected to each other by the connection member, the control gate electrodes being pierced by two of the semiconductor pillars arranged along the second direction;

forming another conducting film on the stacked body;

making other through-holes in the another conducting film in regions directly above the through-holes;

forming a gate insulating film on inner faces of the other through-holes;

filling a semiconductor material into interiors of the other through-holes to form other semiconductor pillars connected to the semiconductor pillars;

dividing the another conducting film to form a plurality of selection gate electrodes aligned in the first direction;

forming a plurality of source lines aligned in the first direction and connected to upper end portions of some of the other semiconductor pillars; and

forming a plurality of bit lines aligned in the second direction and connected to upper end portions of remainder of the other semiconductor pillars.

16. The method according to claim 15, further comprising:

removing the conducting film from an end portion in the second-direction of each of a plurality of blocks set along the second direction,

the dividing into the plurality of the control gate electrodes including organizing the control gate electrodes into the plurality of the blocks, further organizing the control gate electrodes of each of the blocks into two groups, arranging the control gate electrodes of one group alternately with the control gate electrodes of another group along the second direction in each of the blocks, and providing the control gate electrodes of each of the groups with a common connection for the group.

17. The method according to claim 16, wherein the dividing into the plurality of the control gate electrodes includes forming a control gate electrode between two of the adjacent blocks, the control gate electrode being connected to none of the control gate electrodes of the one group and the control gate electrodes of the another group of each of the two blocks.