Conduction switching circuit, conduction switching circuit block, and operating method of conduction switching circuit

• US 20100207679A1
• Filed: 02/16/2010
• Published: 08/19/2010
• Est. Priority Date: 02/19/2009
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Okashita, Tomonori
• Application Number:
  US12/656,784
• Publication Number:
  US 20100207679A1
• Time in Patent Office: Days
• US Class Current: 327/436
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches

Abstract

An object is to provide a conduction switching circuit, an operation method of a conduction switching circuit, and a conduction switching circuit block, which can prevent a leakage of a high frequency signal without insertion loss of a reactance. A conduction switching circuit includes a first MOSFET, a second MOSFET connected to the first MOSFET via a first node, and a first control terminal connected to the first node. The first MOSFET and the second MOSFET are provided so as to be electrically connected in series at ON state. The first control terminal is configured to apply a voltage to the first node so that capacitance of the first MOSFET and the second MOSFET is decreased when the first MOSFET and the second MOSFET are OFF state.

Claims

1. A conduction switching circuit, comprising:

a first MOSFET;

a second MOSFET connected to said first MOSFET via a first node; and

a first control terminal connected to said first node;

wherein said first MOSFET and said second MOSFET are provided so as to be electrically connected in series at an ON state, and

said first control terminal is configured to apply a voltage to said first node so that capacitance generated in said first MOSFET and said second MOSFET is decreased when said first MOSFET and said second MOSFET are an OFF state.

2. The conduction switching circuit according to claim 1, further comprising, a third MOSFET which is connected to said second MOSFET via a second node,

wherein said second MOSFET and said third MOSFET are connected so as to be in series at the ON state, and

said first control terminal is connected to said second node and configured to apply a voltage to said second node so that capacitance of said second MOSFET and said third MOSFET is decreased when said first MOSFET, said second MOSFET, and said third MOSFET are the OFF state.

3. The conduction switching circuit according to claim 1, wherein said first control terminal is connected to said first node via a first resistor whose size is set so that a signal passing through said first node is not leaked to said first control terminal at the ON state.

4. The conduction switching circuit according to claim 1, wherein back gates of said first MOSFET and said second MOSFET are respectively grounded via a resistor of 10 KΩ

or more.

5. The conduction switching circuit according to claim 1, wherein back gates of said first MOSFET and said second MOSFET are respectively connected to a common potential terminal which is different from the ground, via a resistor of 10 KΩ

or more.

6. The conduction switching circuit according to claim 5, wherein said common potential terminal is configured to apply a voltage to said back gates of said first MOSFET and said second MOSFET so that capacitance generated in said first MOSFET and said second MOSFET is decreased at the OFF state.

7. The conduction switching circuit according to claim 1, wherein each of said first MOSFET and said second MOSFET has three terminals of source, drain, and gate, and does not have a back gate terminal.

8. The conduction switching circuit according to claim 1, further comprising, a second control terminal which is connected to a gate of said first MOSFET and a gate of said second MOSFET and applies a voltage to said gates of said first MOSFET and said second MOSFET to control the ON/OFF states of said first MOSFET and said second MOSFET.

9. The conduction switching circuit according to claim 8, wherein said first control terminal and said second control terminal are connected via an inverter circuit.

10. A conduction switching circuit block comprising;

a first conduction switching circuit which is provided between a first end and a second end and connects said first end and said second end at the ON state; and

a second conduction switching circuit which is provided between the ground and said second end and connects said second end to the ground at the ON state;

wherein each of said first conduction switching circuit and said second conduction switching circuit is the conduction switching circuit according to claim 1.

11. The conduction switching circuit block according to claim 10, wherein said first control terminal in said first conduction switching circuit is connected to said first control terminal in said second conduction switching circuit, via an inverter circuit.

13. The conduction switching circuit according to the claim 2, wherein a gate width of said first MOSFET and a gate width of said third MOSFET are larger than a gate width of said second MOSFET.

12. An operation method of a conduction switching circuit having a first MOSFET, a second MOSFET connected to said first MOSFET via a first node, and a first control terminal connected to said first node, wherein said first MOSFET and said second MOSFET are connected in series at the ON state, comprising:

controlling said first MOSFET and said second MOSFET to be the OFF states;

applying a voltage to said first node so that parasitic capacitance generated in said first MOSFET and said second MOSFET is decreased when said first MOSFET and said second MOSFET are the OFF state.

14. A conduction switching circuit, comprising:

a plurality of MOSFETs provided between a fist end and a second end so as to be electrically connected in series at an ON state; and

a first control terminal connected to a plurality of nodes existing between said plurality of MOSFETs;

wherein said first control terminal is configured to apply a voltage to each of said plurality of nodes so that capacitance generated in said plurality of MOSFETs is decreased when said plurality of MOSFETs are OFF state,

said plurality of MOSFETs include;

a first MOSFET connected to said first end;

a third MOSFET connected to said second end; and

a plurality of second MOSFET provided between said first MOSFET and said third MOSFET, and

a gate width of said first MOSFET and a gate width of said third MOSFET are larger than a gate width of each of said plurality of second MOSFETs.

15. A conduction switching circuit, comprising:

a plurality of MOSFETs provided between a fist end and a second end so as to be electrically connected in series at an ON state; and

a first control terminal connected to a plurality of nodes existing between said plurality of MOSFETs;

wherein said first control terminal is configured to apply a voltage to each of said plurality of nodes so that capacitance generated in said plurality of MOSFETs is decreased when said plurality of MOSFETs are OFF state,

said plurality of MOSFETs include;

a first MOSFET connected to said first end;

a third MOSFET connected to said second end; and

a plurality of second MOSFET provided between said first MOSFET and said third MOSFET, and

threshold voltages of said first MOSFET and said third MOSFET are set so as to be different from a threshold voltage of each of said plurality of second MOSFETs.