CONFIGURABLE INTEGRATED CIRCUIT WITH BUILT-IN TURNS

• US 20100210077A1
• Filed: 05/03/2010
• Published: 08/19/2010
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Andre Rohe, Steve Teig
• Inventors: Teig, Steven, Rohe, Andre
• Granted Patent: US 7,994,817 B2
• Time in Patent Office: Days
• US Class Current: 438/129
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments of the invention provide configurable integrated circuits (“IC'"'"'s”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC'"'"'s wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g., buffer circuits), while other direct connections do not have any intervening circuits. Also, in some embodiments, the nodes in the configurable array are all similar (e.g., have the same set of circuit elements and same internal wiring between the circuit elements).

Claims

1-20. -20. (canceled)

21. A method of fabricating an integrated circuit (“

IC”

) comprising;

defining an array of at least fifty configurable nodes, said array having a plurality of rows and a plurality of columns;

defining a plurality of sets of wire segments connecting a plurality of the configurable nodes; and

fabricating said IC to include said array of at least fifty configurable nodes and said plurality of sets of wire segments, wherein at least one particular set of wire segments connects two offset configurable nodes in the array without using intervening interconnect circuits, wherein two configurable nodes are offset when they are not in a same row or column in the array and are at least three rows or at least three columns apart.

22. The method of claim 21, wherein the plurality of sets of wire segments is a first plurality of sets of wire segments and includes a subgroup comprising a second plurality of sets of wire segments that each connect one pair of offset nodes that are separated in the array by at least three rows and at least one column, or at least three columns and at least one row.

23. The method of claim 22, wherein the plurality of sets of wire segments of the subgroup are arranged in a repetitive architecture across the node array.

24. The method of claim 22, wherein the plurality of sets of wire segments of the subgroup are symmetrically arranged across the node array.

25. The method of claim 22, wherein the plurality of sets of wire segments of the subgroup are in a plurality of groups of connections, wherein at least a first group of connections are symmetrically arranged on the node array with respect to a second group of connections.

26. The method of claim 22, wherein the plurality of sets of wire segments of the subgroup are arranged across the node array in a nested architecture.

27. The method of claim 22, wherein the plurality of sets of wire segments of the subgroup are asymmetrically arranged across the node array.

28. The method of claim 22, wherein at least one set of wire segments in said subgroup includes an intervening buffer circuit.

29. The method of claim 21, wherein the particular set of wire segments includes two different segments that are on two different wiring layers of the IC.

30. The method of claim 21, wherein the particular set of wire segments includes two different segments that are connected by a via.

31. The method of claim 21, wherein the nodes are configurable interconnect circuits.

32. A method of fabricating an integrated circuit (“

IC”

) comprising;

defining a plurality of configurable interconnect circuits arranged in an array having a plurality of rows and a plurality of columns;

defining a plurality of sets of wire segments connecting the plurality of the configurable interconnect circuits; and

fabricating said IC to include said plurality of configurable interconnect circuits and said plurality of sets of wire segments, wherein at least one set of wire segments connects two offset configurable interconnect circuits in the array that are separated in the array by at least three rows and at least one column, or at least three columns and at least one row without using any intervening interconnect circuits.

33. The IC of claim 32, wherein said at least one set of wire segments comprises a plurality of sets of wire segments that are symmetrically arranged across the IC.

34. A method of fabricating an integrated circuit (“

IC”

) comprising;

defining a plurality of configurable logic circuits arranged in an array having a plurality of rows and a plurality of columns;

defining a plurality of sets of wire segments connecting the plurality of the configurable logic circuits; and

fabricating said IC according to said defined plurality of configurable logic circuits and said plurality of sets of wire segments, wherein at least one set of wire segments connects two offset configurable logic circuits in the array that are separated in the array by at least three rows and at least one column, or at least three columns and at least one row without using any intervening interconnect circuits that have outputs that connect to more than one configurable circuit.

35. The method of claim 34, wherein the plurality of sets of wire segments of the subgroup are arranged across the node array in a nested architecture.

36. The method of claim 34, wherein the plurality of sets of wire segments of the subgroup are asymmetrically arranged across the node array.