CLOCK AND POWER FAULT DETECTION FOR MEMORY MODULES

• US 20100211765A1
• Filed: 04/29/2010
• Published: 08/19/2010
• Est. Priority Date: 10/25/2006
• Status: Active Grant

• Current Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Original Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Inventors: Amidi, Mike H., Kolli, Satyadev
• Granted Patent: US 8,644,105 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

Claims

1. A method for maintaining memory contents in a volatile memory of a memory module, wherein the memory module is coupled with a computer system, the method comprising:

detecting a clock status in the memory module;

operating a memory module controller having a memory control state machine to receive the detected clock status and to change states based on the detected clock status;

generating a memory module internal clock to provide a memory module integrated backup clock; and

operating a clock multiplexer to receive the memory module integrated backup clock and an external system clock and to provide a memory module clock selected from the module integrated backup clock and the external system clock.

2. The method of claim 1, further comprising:

detecting a voltage status in the memory module;

maintaining a power storage device in the memory module to provide a memory module integrated backup power supply;

operating the memory module controller having a memory control state machine to receive the detected voltage status and to change states based on the detected voltage status; and

operating a power multiplexer in the memory module to receive power from the power storage device and from the system power supply and to provide power to the memory module including to the volatile memory, the power multiplexer operable to communicate power from the system power to the volatile memory when the system has sufficient power to maintain memory contents in the volatile memory, and to communicate power from the memory module integrated backup power supply when the system does not have sufficient power to maintain memory contents in the volatile memory.

25. The method of claim 2, wherein the operating of the power multiplexer further comprise:

controlling a first series of two drain coupled transistors coupled between an output of the power storage device and a power supply input of the volatile memory in response to a first comparison signal; and

controlling a second series of two drain coupled transistors coupled between the system power supply and the power supply input of the volatile memory in response to a second comparison signal;

the first series of coupled transistors controlled by the first comparison signal and the second series of transistors controlled by the second comparison that is a complement of the first comparison signal; and

the controlling of the first and second series of transistors being so that conduction through the first series of transistors and the second series of transistors occurs only through one of the first series of transistors and the second series of transistors at the same time.

26. The method of claim 25, wherein:

the controlling of the first series of two drain coupled transistors comprises controlling of a first series of two drain coupled MOSFET transistors; and

the controlling of the second series of two drain coupled transistors comprise the controlling of a second series of two drain coupled MOSFET transistors.

3. A memory module device that maintains memory contents in a volatile memory of the memory module, wherein the memory module is coupled with a computer system, the device comprising:

a clock detection circuit for detecting a clock status in the memory module;

a memory module controller having a memory control state machine operable to receive the detected clock status and to change states based on the detected clock status;

a memory module internal clock generation circuit for generating a memory module integrated backup clock; and

a clock multiplexer circuit operable to receive the memory module integrated backup clock and an external system clock and to provide a memory module clock selected from the module integrated backup clock and the external system clock.

4. The device of claim 3, further comprising:

a voltage detection circuit for detecting a voltage status in the memory module;

a power storage device in the memory module to provide a memory module integrated backup power supply;

the memory module controller memory control state machine being further operable to receive the detected voltage status and to change states based on the detected voltage status; and

a power multiplexer in the memory module operable to receive power from the power storage device and from the system power supply and to provide power to the memory module including to the volatile memory, the power multiplexer operable to communicate power from the system power to the volatile memory when the system has sufficient power to maintain memory contents in the volatile memory, and to communicate power from the memory module integrated backup power supply when the system does not have sufficient power to maintain memory contents in the volatile memory.

5. The device of claim 4, wherein:

the controller is implemented as a processor system on a chip.

6. The device of claim 4, wherein:

the memory control state machine is implemented as a complex programmable logic device.

7. The device of claim 4, wherein:

the volatile memory is DDR2 SDRAM.

8. The device of claim 4, wherein:

the volatile memory is DDR SDRAM.

9. The device of claim 4, wherein the detecting a voltage and a clock in the memory module comprises detecting the voltage in a voltage detection circuit and the clock in a clock detection circuit.

10. The device of claim 4, wherein the operating of the clock multiplexer and the power multiplexer are controlled by a memory control state machine in the memory module that receives the detected voltage and the detected clock.

11. The device of claim 4, wherein the power storage device comprises a battery.

12. The device of claim 4, wherein the detected voltage is a system power supply derived voltage, and the detected clock is a system clock.

13. The device of claim 4, wherein the state machine is configured to perform a method comprising:

initializing a state machine with a reset signal at idle state;

moving the state machine into a ready state when the system is armed in response to an enable signal;

moving the state machine to a start state in response to a start signal;

moving the state machine to a wait state from the start state, in response to an enable signal;

starting a first timer when in the wait state and in response to a signal from the first timer advancing the state machine to a precharge state;

moving the state machine from the precharge state automatically to another wait state and starting a second timer;

moving the state machine to a self-refresh entry state in response to a signal from the second timer, with self-refresh initiated for the memory module;

automatically moving the state machine to self refresh state and remaining in the self refresh state so that there automatically self-refreshing the memory module to maintain the contents of the memory; and

moving the state machine back to the idle state in response to either a reset signal or an exit signal to end the self-refresh process when the self-refresh process is no longer needed.

21. The device of claim 4, wherein the power multiplexer further comprises:

a first series of two drain coupled transistors coupled between an output of the power storage device and a power supply input of the volatile memory; and

a second series of two drain coupled transistors coupled between the system power supply and the power supply input of the volatile memory;

the first series of coupled transistors controlled by a comparison signal and the second series of transistors controlled by a complement of the comparison signal so that conduction occurs only through one of the first series of transistors and the second series of transistors at the same time.

22. The device of claim 21, wherein the first series of two drain coupled transistors comprise a first series of two drain coupled MOSFET transistors;

and the second series of two drain coupled transistors comprise a second series of two drain coupled MOSFET transistors.

14. A method for maintaining memory contents in a volatile memory of a memory module, wherein the memory module is coupled with a computer system, the method comprising:

detecting a voltage status in the memory module;

maintaining a power storage device in the memory module to provide a memory module integrated backup power supply;

operating the memory module controller having a memory control state machine to receive the detected voltage status and to change states based on the detected voltage status; and

operating a power multiplexer in the memory module to receive power from the power storage device and from the system power supply and to provide power to the memory module including to the volatile memory, the power multiplexer operable to communicate power from the system power to the volatile memory when the system has sufficient power to maintain memory contents in the volatile memory, and to communicate power from the memory module integrated backup power supply when the system does not have sufficient power to maintain memory contents in the volatile memory.

15. A memory module device that maintains memory contents in a volatile memory of the memory module, wherein the memory module is coupled with a computer system, the device comprising:

a voltage detection circuit for detecting a voltage status in the memory module;

a power storage device in the memory module to provide a memory module integrated backup power supply;

a memory module controller having a memory control state machine to receive the detected voltage status and to change states based on the detected voltage status; and

a power multiplexer in the memory module operable to receive power from the power storage device and from the system power supply and to provide power to the memory module including to the volatile memory, the power multiplexer operable to communicate power from the system power to the volatile memory when the system has sufficient power to maintain memory contents in the volatile memory, and to communicate power from the memory module integrated backup power supply when the system does not have sufficient power to maintain memory contents in the volatile memory.

23. The device of claim 15, wherein the power multiplexer further comprises:

a first series of two drain coupled transistors coupled between an output of the power storage device and a power supply input of the volatile memory; and

a second series of two drain coupled transistors coupled between the system power supply and the power supply input of the volatile memory;

the first series of coupled transistors controlled by a comparison signal and the second series of transistors controlled by a complement of the comparison signal so that conduction occurs only through one of the first series of transistors and the second series of transistors at the same time.

24. The device of claim 23, wherein the first series of two drain coupled transistors comprise a first series of two drain coupled MOSFET transistors;

and the second series of two drain coupled transistors comprise a second series of two drain coupled MOSFET transistors.

16. A method for maintaining power and clock in a memory module including a volatile memory, wherein the memory module is coupled to a bus in a computer system having a system clock and a system power supply, the method comprising:

detecting a voltage and a clock in the memory module;

operating a controller having a memory control state machine in the memory module to receive the detected voltage and the detected clock;

maintaining a power storage device in the memory module to provide a memory module integrated backup power supply;

maintaining a clock generation circuit in the memory module to provide a memory module integrated backup clock; and

operating a power multiplexer in the memory module to receive power from the power storage device and from the system power supply and to provide power to the memory module including to the volatile memory, the power multiplexer operable to communicate power from the system power to the volatile memory when the system has sufficient power to maintain memory contents in the volatile memory, and to communicate power from the memory module integrated backup power supply when the system does not have sufficient power to maintain memory contents in the volatile memory;

operating a clock multiplexer to receive the memory module integrated backup clock and a system clock and to provide a memory module clock selected from the module integrated backup clock and the system clock.

17. A memory module, comprising:

a voltage detection circuit;

a clock detection circuit;

a controller coupled to the voltage detection circuit and the clock detection circuit;

a memory control state machine coupled to the controller;

a volatile memory coupled to the memory control state machine;

a charge or energy storage device; and

a power multiplexer coupled to receive a power supply of the charge or energy storage device and a power supply of a surrounding system and to provide a power supply to the volatile memory; and

a clock multiplexer coupled to receive a memory module-integrated battery backup clock and a system clock and to provide a memory module clock.

18. A unitary memory module device comprising:

a memory control state machine;

a controller coupled to a voltage level detection circuit and a clock signal detection circuit and receiving state information from the memory control state machine;

a volatile memory coupled to the controller;

a backup power supply coupled to the controller;

a power multiplexer coupled to receive a backup power from the backup power supply and an external power supply of a surrounding system and to provide a power supply to the volatile memory;

a clock multiplexer coupled to receive a memory module-integrated battery backup clock and a system clock and to provide a memory module clock; and

the volatile memory, the controller, the backup power supply, the power multiplexer and the clock multiplexer are all collectively included in the unitary memory module.

19. The device of claim 18, wherein the state machine is configured to perform a method comprising:

initializing a state machine with a reset signal at idle state;

moving the state machine into a ready state when the system is armed in response to an enable signal;

moving the state machine to a start state in response to a start signal;

moving the state machine to a wait state from the start state, in response to an enable signal;

starting a first timer when in the wait state and in response to a signal from the first timer advancing the state machine to a precharge state;

moving the state machine from the precharge state automatically to another wait state and starting a second timer;

moving the state machine to a self-refresh entry state in response to a signal from the second timer, with self-refresh initiated for the memory module;

automatically moving the state machine to self refresh state and remaining in the self refresh state so that there automatically self-refreshing the memory module to maintain the contents of the memory; and

moving the state machine back to the idle state in response to either a reset signal or an exit signal to end the self-refresh process when the self-refresh process is no longer needed.

20. A method of using a state machine for a memory module triggering memory refresh operations of a memory in or coupled with the memory module for controlling refresh of the memory when the memory is not subject of operations in a system mode including in a system power fail mode and where the memory refresh operations are implemented without benefit of other parts of a system, the method comprising:

initializing a state machine with a reset signal at idle state;

moving the state machine into a ready state when the system is armed in response to an enable signal;

moving the state machine to a start state in response to a start signal;

moving the state machine to a wait state from the start state, in response to an enable signal;

starting a first timer when in the wait state and in response to a signal from the first timer advancing the state machine to a precharge state;

moving the state machine from the precharge state automatically to another wait state and starting a second timer;

moving the state machine to a self-refresh entry state in response to a signal from the second timer, with self-refresh initiated for the memory module;

automatically moving the state machine to self refresh state and remaining in the self refresh state so that there automatically self-refreshing the memory module to maintain the contents of the memory; and

moving the state machine back to the idle state in response to either a reset signal or an exit signal to end the self-refresh process when the self-refresh process is no longer needed.