NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE

• US 20100220533A1
• Filed: 05/04/2010
• Published: 09/02/2010
• Est. Priority Date: 07/10/2007
• Status: Active Grant

• Current Assignee: Changyuan Chen, Dana Lee, Ya-Fen Lin
• Original Assignee: Changyuan Chen, Dana Lee, Ya-Fen Lin
• Inventors: Lin, Ya-Fen, Lee, Dana, Chen, Changyuan
• Granted Patent: US 8,164,135 B2
• Time in Patent Office: Days
• US Class Current: 365/185.270
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

Claims

1-14. -14. (canceled)

15. An array of flash memory structures, said array comprising:

a semiconductor substrate of a first conductivity type; and

a plurality of structures, each structure comprising;

a non-diffused channel region within the semiconductor substrate through which electron flow may be induced, in a first direction, by application of voltage to gate elements disposed above the channel region;

a plurality of floating gates, spaced apart from one another, each insulated from the channel region;

a plurality of control gates, spaced apart from one another, each insulated from the channel region, each control gate being between a first floating gate and a second floating gate, and being capacitively coupled to the first floating gate and the second floating gate, wherein each control gate and pair floating gates to which the control gate is capacitively coupled form a subcell;

and a plurality of assist gates, spaced apart from one another, each insulated from the channel region, each assist gate being between and insulated from a first subcell and a second subcell;

wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath;

wherein structures adjacent to one another in a second direction, substantially perpendicular to the first direction, have the assist gate connected to one another in the first direction, and the control gate connected to one another in the second direction.

16. The array of claim 15 wherein a line of substrate region (bit line) laying beneath a row of control gates in a second direction includes an actual diffused junction at an end of the line.

17. The array of claim 15 wherein, with regard to control gates adjacent to each other in the first direction, the channel region lies between a first substrate under a first control gate and a second substrate region under a second control gate.

21. The array of claim 15 wherein each floating gate is between a control gate and an assist gate.

22. The array of claim 15 wherein each floating gate is immediately adjacent a channel region associated with the subcell in which the floating gate is located.

23. The array of claim 22 wherein the floating gate is disposed adjacent the substrate, a control gate, and an assist gate, and insulated therefrom with insulation material having a thickness that permits Fowler-Nordheim tunneling.

24. The array of claim 15 wherein each control gate is substantially T shaped.

25. The array of claim 24 wherein each control gate includes a lower portion immediately adjacent the channel region and two upper portions.

26. The array of claim 25 wherein each floating gate is located between an upper portion of a control gate and the channel region.

27. The array of claim 25 wherein each upper portion is immediately adjacent to one of the floating gates to which the control gate is capacitively coupled.

28. The array of claim 15 wherein the channel region defines a path used for one or both of reading or programming a floating gate.

29. The array of claim 15 wherein structures connected electrically to one another in series and co-linear to one another terminate at a first end and at a second end, with said first end addressed by a first address, and the second end addressed by a second address, different from the first address.

18-20. -20. (canceled)

30. A method of erasing a plurality of floating gates arranged in a column direction in an array of flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of AND structures with each structure having:

a non-diffused channel region within the semiconductor substrate through which electron flow may be induced by application of voltage to gate elements disposed above the channel region, with electron flow in the channel region being in a row direction substantially perpendicular to the column direction;

a plurality of floating gates, spaced apart from one another, each insulated from the substrate;

each AND structure further having a control gate insulated from the substrate, the control gate being between a first floating gate and a second floating gate, and being capacitively coupled to the first floating gate and the second floating gate; and

an assist gate insulated from the substrate, the assist gate being between a first floating gate in a first AND structure and a second floating gate in a second AND structure;

whereby a floating gate is between an assist gate and a control gate;

wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath;

wherein the AND structures adjacent to one another in the row direction, have assist gates connected to one another in the row direction, and AND structures adjacent to each other in the column direction have the control gate connected to one another in the column direction;

said method of erasing comprising;

applying a non-positive voltage to a selected column of control gates immediately adjacent to one side of select floating gates in the selected column; and

applying a high positive voltage to a selected row of assist gates immediately adjacent to another side of the select floating gates in the selected column;

wherein a first column of floating gates between the selected column of control gates and the selected row of assist gates are erased by charges from the first column of floating gates tunneling to the selected row of assist gates.

31. The method of claim 30 further comprising applying ground voltage to all the columns of control gates not selected and applying ground voltage to all the rows of assist gates not selected.

32. The method of claim 31 further comprising applying ground voltages to lines of substrate region laying beneath adjacent columns of control gates forming a channel therebetween.

33. The method of claim 30, further comprising a floating gate having a tip directed to a control gate for facilitating the removal of charges from the floating gate to the control gate.

34. The method of claim 30 further comprising:

applying a non-positive voltage to a column of control gates immediately adjacent to a side of a second column of floating gates, other than the first column of floating gates, wherein the second column of floating gates is immediately adjacent to the column of control gates to which a ground voltage is applied;

wherein the first column of floating gates and second column of floating gates are erased simultaneously by charges from the first and second columns of floating gates tunneling to the selected row(s) of assist gates.

35. The method of claim 30, wherein a first AND structure and an adjacent AND structure are erased in connection with each other by applying a non-positive voltage to control gates of both AND structures such that a floating gate of the first AND structure and a floating gate of an adjacent AND structure are erased by tunneling to a common assist gate located therebetween.

36. A method of erasing a plurality of floating gates arranged in a column direction in an array of flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of AND structures with each structure having:

a non-diffused channel region within the semiconductor substrate through which electron flow may be induced by application of voltage to gate elements disposed above the channel region, with electron flow in the channel region being in a row direction substantially perpendicular to the column direction;

a plurality of floating gates, spaced apart from one another, each insulated from the substrate;

each AND structure further having a control gate insulated from the substrate, the control gate being between a first floating gate and a second floating gate, and being capacitively coupled to the first floating gate and the second floating gate; and

an assist gate insulated from the substrate, the assist gate being between a first floating gate in a first AND structure and a second floating gate in a second AND structure;

whereby a floating gate is between an assist gate and a control gate;

wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath;

wherein the AND structures adjacent to one another in the row direction, have assist gates connected to one another in the row direction, and AND structures adjacent to each other in the column direction have the control gate connected to one another in the column direction;

said method of erasing comprising;

applying a high negative voltage to a selected column of control gates immediately adjacent to one side of select floating gates in the selected column; and

applying a non-negative voltage to a selected row of assist gates;

wherein a first column of floating gates adjacent to the selected column of control gates are erased by charges from the first column of floating gates tunneling to the substrate.

37. The method of claim 36 further comprising applying ground voltage to all the columns of control gates not selected and applying ground voltage to all the rows of assist gates not selected.

38. The method of claim 36 further comprising applying ground voltages to lines of substrate region laying beneath adjacent columns of control gates forming a channel therebetween.

39. A method of erasing a plurality of floating gates arranged in a column direction in an array of flash memory structures, said array formed in a semiconductor substrate of a first conductivity type and having a plurality of AND structures with each structure having:

a non-diffused channel region within the semiconductor substrate through which electron flow may be induced by application of voltage to gate elements disposed above the channel region, with electron flow in the channel region being in a row direction substantially perpendicular to the column direction;

a plurality of floating gates, spaced apart from one another, each insulated from the substrate;

each AND structure further having a control gate insulated from the substrate, the control gate being between a first floating gate and a second floating gate, and being capacitively coupled to the first floating gate and the second floating gate; and

an assist gate insulated from the substrate, the assist gate being between a first floating gate in a first AND structure and a second floating gate in a second AND structure;

whereby a floating gate is between an assist gate and a control gate;

wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath;

wherein the AND structures adjacent to one another in the row direction, have assist gates connected to one another in the row direction, and AND structures adjacent to each other in the column direction have the control gate connected to one another in the column direction;

said method of erasing comprising;

applying a high positive voltage to a selected column of control gates immediately adjacent to one side of select floating gates in the selected column; and

applying a non-positive voltage to a selected row of assist gates immediately adjacent to another side of the select floating gates in the selected column;

wherein a first column of floating gates between the selected column of control gates and the selected row of assist gates are erased by charges from the first column of floating gates tunneling to the selected column of control gates.

40. The method of claim 39 further comprising applying ground voltage to all columns of control gates not selected and applying ground voltage to all rows of assist gates not selected.

41. The method of claim 39 further comprising applying ground voltages to lines of substrate region laying beneath adjacent columns of control gates forming a channel therebetween.

42. The method of claim 39, further comprising a floating gate having a tip directed to a control gate for facilitating the removal of charges from the floating gate to the control gate.

43. (canceled)

44. A method of programming a select floating gate, in an array of AND flash memory structures, the array formed in a semiconductor substrate of a first conductivity type and having a plurality of AND structure with each AND structure having:

a non-diffused channel region within the semiconductor substrate through which electron flow may be induced by application of voltage to gate elements disposed above the channel region, with electron flow in the channel region being in a row direction substantially perpendicular to the column direction;

a plurality of floating gates, spaced apart from one another, each insulated from the substrate;

each AND structure further having a control gate insulated from the substrate, the control gate being between a first floating gate and a second floating gate, and being capacitively coupled to the first floating gate and the second floating gate; and

an assist gate insulated from the substrate, the assist gate being between a first floating gate in a first AND structure and a second floating gate in a second AND structure;

whereby a floating gate is between an assist gate and a control gate;

wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath;

wherein the AND structures adjacent to one another in the row direction, have assist gates connected to one another in the row direction, and AND structures adjacent to each other in the column direction have the control gate connected to one another in the column direction;

said method of programming comprising;

applying a first non-positive voltage to a first line of substrate region laying beneath control gates within first subcells adjacent to each other in a column direction;

applying a second voltage to a second line of substrate region laying beneath control gates of second subcells adjacent to each other in a column direction;

applying a third voltage to the assist gate between the first subcell and the second subcell, which contains a select floating gate to program;

the third voltage being sufficient to turn on the third channel region over which the assist gate is positioned;

applying a fourth voltage to the second control gate of the second subcell, the fourth voltage being sufficient to turn on the second channel region over which the select floating get is positioned;

applying a fifth voltage to the first control gate of the first subcell;

the fifth voltage sufficient to couple enough voltage to a floating gate of the first subcell located above the first channel region to turn on the first channel region, and thereby program the select floating gate.

45. The method of programming of claim 44 wherein the first line of substrate region is to one side of the select floating gate;

and the second line of substrate region to another side of the select floating gate; and

wherein the first voltage is lower than the second voltage.

46. The method of claim 45 wherein said second line of substrate region of the first AND structure is connected in common to a second line of a substrate region of a second AND structure immediately adjacent to the first AND structure in the row direction.