ELECTRONIC DEVICES FORMED OF TWO OR MORE SUBSTRATES BONDED TOGETHER, ELECTRONIC SYSTEMS COMPRISING ELECTRONIC DEVICES AND METHODS OF MAKING ELECTRONIC DEVICES

• US 20100232220A1
• Filed: 03/10/2009
• Published: 09/16/2010
• Est. Priority Date: 03/10/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Meade, Roy E.
• Granted Patent: US 7,969,774 B2
• Time in Patent Office: Days
• US Class Current: 365/171
• CPC Class Codes: B82Y 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: G11C 11/14 using thin-film elements
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 19/0808 using magnetic domain propagation
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/112 : directly combined with via connections
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/144 : Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 2201/09381 : Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component notches in edge pads H05K2201/09181
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/36 : Assembling printed circuits with other printed circuits H05K7/142 takes precedence
• CPC Class Codes: H05K 3/4697 : having cavities, e.g. for mounting components H05K3/4691 takes precedence
• CPC Class Codes: H05K 7/04 : on conductive chassis
• CPC Class Codes: Y10S 977/932 : for electronic or optoelectronic application
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base

Abstract

Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads are positioned on a surface of the first substrate and comprise a width extending over at least two of the plurality of conductive traces. A plurality of vias extend from adjacent at least some of the conductive traces to the plurality of bond pads. The second substrate is bonded to the first substrate and comprises circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps. Memory devices and related methods of forming electronic devices and memory devices are also disclosed, as are electronic systems.

Claims

1. An electronic device, comprising:

a first substrate comprising circuitry including a plurality of conductive traces extending at least substantially parallel to each other through a portion of the first substrate, a plurality of bond pads positioned on a surface of the first substrate and comprising a width extending over at least two of the plurality of conductive traces, and a plurality of vias extending from adjacent at least some conductive traces of the plurality of conductive traces to bond pads of the plurality of bond pads;

a second substrate bonded to the first substrate, the second substrate comprising circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps.

2. The electronic device of claim 1, wherein the plurality of conductive traces comprise a plurality of magnetic shift registers comprising a plurality of domains, and the plurality of vias comprise a plurality of magnetic tunneling junctions.

3. The electronic device of claim 1, wherein the circuitry of the second substrate comprises at least one of a charge pump, a decode and addressing circuit, a sense amplifier and an I/O circuit.

4. The electronic device of claim 1, wherein the plurality of conductive traces are disposed at a pitch of less than 100 nanometers, and wherein the plurality of bond pads each comprise an area of 2,000 μ

m² or greater.

5. The electronic device of claim 1, wherein at least one bond pad of the plurality of bond pads comprises:

a first diode biased in a first direction and adjacent to an upper conductive pad and a first lower conductive pad, the first lower conductive pad coupled to a via of the plurality of vias; and

a second diode biased in a second, opposing direction and adjacent to the upper conductive pad and a second lower conductive pad, the second lower conductive pad coupled to another via of the plurality of vias.

6. The electronic device of claim 1, wherein:

the plurality of bond pads are positioned in a pattern on the surface of the first substrate comprising one of a bond raster pattern and a bond shift pattern; and

the bond pads comprise at least one shape selected from the group consisting of square, rectangular, hexagonal and triangular.

7. A memory device comprising a first substrate, the first substrate comprising:

a plurality of magnetic tracks comprising a plurality of domains;

a plurality of magnetic tunneling junctions proximate to the plurality of magnetic tracks and extending to a location adjacent a surface of the first substrate; and

a plurality of bond pads on the surface of the first substrate, each bond pad of the plurality of bond pads electrically coupled to a magnetic tunneling junction of the plurality of magnetic tunneling junctions.

8. The memory device of claim 7, further comprising a second substrate comprising support circuitry, the second substrate being bonded to the plurality of bond pads with a plurality of conductive bumps.

9. The memory device of claim 8, wherein the support circuitry of the second substrate comprises at least one of a charge pump, a decode and addressing circuit, a sense amplifier and an I/O circuit.

10. The memory device of claim 7, wherein at least one bond pad of the plurality of bond pads comprises:

an upper conductive pad coupled to a first diode and a second diode, the first diode being biased in a direction opposite to the bias of the second diode;

a first lower conductive pad coupled to the first diode and to a via of the plurality of vias; and

a second lower conductive pad coupled to the second diode and to another via of the plurality of vias.

11. The memory device of claim 7, wherein bond pads of the plurality of bond pads comprise a width extending over at least two magnetic tracks of the plurality of magnetic tracks.

12. The memory device of claim 7, wherein the bond pads are configured to comprise a shape consisting of at least one of square, rectangular, hexagonal, and triangular.

13. A method of fanning an electronic device, comprising:

forming a first substrate comprising a plurality of conductive traces extending through a portion thereof, a plurality of vias extending from adjacent at least some conductive traces of the plurality of conductive traces to a surface of the first substrate, and a plurality of bond pads on the surface of the first substrate and adjacent to a via of the plurality of vias, each bond pad of the plurality of bond pads comprising a width extending over at least two conductive traces of the plurality of conductive traces;

forming a second substrate comprising circuitry;

attaching a second substrate to the first substrate with a plurality of conductive bumps coupled to the plurality of bond pads on the first surface of the first substrate and to the circuitry of the second substrate.

14. The method of claim 13, wherein forming the first substrate further comprises:

forming the plurality of conductive traces as a plurality of magnetic shift registers, each magnetic shift register comprising a plurality of domains; and

forming the plurality of vias configured as magnetic tunneling junctions.

15. The method of claim 14, wherein forming the first substrate comprises forming the first substrate at a temperature below about 450°

C., and wherein forming the second substrate comprises forming the second substrate at a temperature above about 450°

C.

16. The method of claim 13, wherein forming the first substrate comprising the plurality of bond pads on the surface of the first substrate comprises forming the plurality of bond pads comprising at least one shape selected from the group of shapes consisting of square, rectangular, hexagonal and triangular.

17. The method of claim 13, wherein forming the first substrate comprising the plurality of bond pads on the surface of the first substrate comprises positioning the plurality of bond pads on the surface of the first substrate in a pattern comprising one of a bond raster pattern and a bond shift pattern.

18. The method of claim 13, wherein forming the first substrate comprising the plurality of bond pads on the surface of the first substrate comprises:

disposing a first lower conductive pad coupled to a via of the plurality of vias;

disposing a second lower conductive pad coupled to another via of the plurality of vias;

disposing a first diode biased in a first direction on the first lower conductive pad;

disposing a second diode biased in a second, opposite direction on the second lower conductive pad; and

disposing an upper conductive pad over the first diode and the second diode.

19. A method of forming a memory device, comprising:

forming a plurality of conductive traces in a first substrate, the plurality of conductive traces configured as magnetic shift registers comprising a plurality of domains;

forming a plurality of vias comprising magnetic tunneling junctions extending from a surface of the first substrate to proximate the plurality of magnetic shift registers;

forming a plurality of bond pads, each bond pad of the plurality of bond pads coupled to a via of the plurality of vias.

20. The method of claim 19, further comprising:

forming support circuitry in a second substrate; and

coupling the support circuitry in the second substrate to the plurality of bond pads of the first substrate with a plurality of conductive bumps.

21. The method of claim 20, wherein forming the support circuitry in the second substrate comprises forming at least one of a charge pump, a decode and addressing circuit, a sense amplifier, and an I/O circuit.

22. The method of claim 19, wherein forming the plurality of bond pads comprises patterning the plurality of bond pads to comprise one of a bond raster pattern and a bond shift pattern.

23. The method of claim 19, wherein forming the plurality of bond pads comprises configuring the plurality of bond pads with at least one shape selected from the list consisting of square, rectangular, hexagonal and triangular.

24. The method of claim 19, wherein forming the plurality of bond pads comprises forming a plurality of bond pads, each comprising:

a first diode biased in a first direction coupled to a first lower conductive pad in electrical contact with a via of the plurality of vias;

a second diode biased in a second, opposite direction coupled to a second lower conductive pad in electrical contact with another via of the plurality of vias; and

an upper conductive pad coupled to the first diode and to the second diode.

25. A system, comprising:

at least one processor; and

at least one memory device coupled to the processor, the at least one memory device comprising;

a first substrate comprising a plurality of magnetic tracks including a plurality of domains, a plurality of magnetic tunneling junctions proximate to the plurality of magnetic tracks and extending to a location adjacent a surface of the first substrate, and a plurality of bond pads on the surface of the first substrate, each bond pad of the plurality of bond pads electrically coupled to a magnetic tunneling junction of the plurality of magnetic tunneling junctions; and

a second substrate comprising support circuitry, the second substrate bonded to the plurality of bond pads with a plurality of conductive bumps.