Apparatus comprising artificial neuronal assembly

• US 20100241601A1
• Filed: 03/18/2010
• Published: 09/23/2010
• Est. Priority Date: 03/20/2009
• Status: Active Grant

• Current Assignee: Irvine Sensors Corp., PFG Ip, LLC
• Original Assignee: Irvine Sensors Corp.
• Inventors: Ozguz, Volkan, Carson, John C.
• Granted Patent: US 8,510,244 B2
• Time in Patent Office: Days
• US Class Current: 706/27
• CPC Class Codes: G06N 3/02 Neural networks

Abstract

An artificial synapse array and virtual neural space are disclosed.

More specifically, a cognitive sensor system and method are disclosed comprising a massively parallel convolution processor capable of, for instance, situationally dependent identification of salient features in a scene of interest by emulating the cortical hierarchy found in the human retina and visual cortex.

Claims

1. A virtual neural space comprising:

an electronic synapse array comprising a plurality of electronic neurons each comprising at least one synapse connection,

multiplication and addition circuit means,

storage means for storing and outputting a plurality of changing synapse weight inputs,

wherein selected ones of said synapses having a time-dependent connectivity with selected other ones of said synapses by means of at least one time-dependent reconfigurable connection.

2. A method for providing a virtual neural space comprising:

providing an electronic synapse array comprising a plurality of synapse array inputs, multiplication and addition circuit means and storage means for storing and outputting a plurality of changing synapse weight inputs, wherein selected ones of said synapses have a time-dependent connectivity with selected other ones of said synapses by means of at least one time-dependent reconfigurable synapse,

said array having a first connectivity state at a first time state,

said array having a second connectivity state at a second time state,

changing said first connectivity state to said second connectivity state while remembering said first connectivity state to provide an array data set, and,

outputting said array data set after a time integration step to a storage node.

3. A method for electronically emulating a neural space comprising:

providing a first data input signal and a second data input signal,

providing a synapse array comprising a plurality of nodes, synapses and a plurality of weight spaces and comprising a multiply and add array,

wherein selected ones of said synapses have a time-dependent connectivity with selected other ones of said synapses by means of at least one time-dependent reconfigurable synapse.

associating a predetermined first weight in a first weight space using time-division multiplexing with said first data input signal,

associating of a predetermined second weight in a second weight space using time-division multiplexing with said second data input signal,

selectively emphasizing or deemphasizing said data input signals in said multiply and add array based on said associations,

multiplying said first data input signal with said first weight to produce a first node output comprising a first product,

multiplying said second data input signal with said second weight to produce a second node output comprising a second product,

adding said first product and said second product to produce a convolved output,

comparing said convolved output with a predetermined template to define a template match or template mismatch,

feeding back said template matches or template mismatches to said weight spaces at least once to improve or degrade said template match or mismatch.

4. The method of claim 3 wherein said multiplier array comprises an N×

M analog current mode multiplier.

5. The method of claim 3 wherein said multiplier array comprises an N×

M digital multiplier.

6. An electronic neural space comprising:

means for receiving a set of data signals,

means for associating a predetermined weight in a weight space with each of said data signals using time-division multiplexing for the selective emphasizing or deemphasizing of said data signals in a multiplier array,

wherein a plurality of said nodes comprise a memory cell for the receiving of at least one data signal and at least one weight data,

means for multiplying a plurality of said data signals with at least one of said weights in the analog current mode domain to produce at least two products,

means for adding at least two of said products to produce a convolved output,

means for comparing said convolved output against a predetermined template to define a match or mismatch,

means for feeding back said convolved output to said weight space to enhance or degrade said match or mismatch.

7. The electronic neural space of claim 6 wherein said multiplier comprises an N×

M analog current mode multiplier.

8. The electronic neural space of claim 6 wherein said multiplier comprises a digital multiplier.

9. The electronic neural space of claim 6 further comprising control logic for interface to saccading and foveating means.

10. The electronic neural space of claim 6 wherein said electronic neural space is operating in the sub-threshold CMOS region.

11. The electronic neural space of claim 6 wherein a current digital-to-analog converter receives data from said memory.

12. The electronic neural space of claim 6 wherein said analog multiplier comprises a Gilbert multiplier.

13. The electronic neural space of claim 6 wherein said analog multiplier comprises a four-quadrant Gilbert multiplier.

14. The electronic neural space of claim 6 comprising at least two transverse-mated stacks comprising a plurality of layers of microelectronic circuitry.

15. A cognitive sensor circuit for the emulation of the visual cortex of a human brain comprising:

a first supertile and a second supertile,

said first and second supertiles comprising a plurality of tiles and comprising a supertile processor, supertile memory and a supertile look up table,

said first supertile in electronic communication with said second supertile,

said tiles comprising a plurality of cells and comprising a tile processor, tile memory and a tile look up table,

selected ones of said tiles having a plurality of tile mesh outputs in electronic communication with selected other ones of said tiles,

said cells comprising dedicated image memory and dedicated weight memory and convolution circuit means for performing a convolution kernel mask operation on an image data set representative of a scene,

selected ones of said cells having a plurality of cell mesh outputs in electronic communication with selected other ones of said cells,

root processor circuit means for managing electronic communication between said cell mesh outputs, said tile mesh outputs or said supertile mesh outputs.

16. A method for emulating the visual cortex of a human brain comprising:

providing at least one supertile comprised of a first tile and a second tile said first tile comprising a plurality of first cells and said second tile comprised of a plurality of second cells,

at least one of said plurality of first cells and at least one of said plurality of second cells comprising a plurality of cell mesh outputs wherein selected ones of said plurality of first cells are in communication with selected other ones of said second cells,

providing an image data set representative of a scene,

selecting one or more predetermined image data subsets from said image data set,

receiving said one or more image data subsets to a first cell and to a second cell,

performing concurrent convolution kernel mask operations in each of said first and second cells on said image data subsets to provide a plurality of convolved cell outputs.