LOW VOLTAGE DRIVER SCHEME FOR INTERFEROMETRIC MODULATORS

• US 20100245311A1
• Filed: 01/20/2010
• Published: 09/30/2010
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Mignard, Mark M., Chui, Clarence, Cummings, William, Van Lier, Wilhelmus Johannes Robertus, Lewis, Alan G., Todorovich, Mark M.
• Granted Patent: US 8,736,590 B2
• Time in Patent Office: Days
• US Class Current: 345/208
• CPC Class Codes: G09G 2300/0473 Use of light emitting or modulating elements having two or more stable states when no power is applied
• CPC Class Codes: G09G 2300/06 Passive matrix structure, i.e. with direct application of both column and row voltages to the light emitting or modulating elements, other than LCD or OLED
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/3466 based on interferometric effect

Abstract

A method of driving electromechanical devices such as interferometric modulators includes applying a voltage along a common line to release the electromechanical devices along the common line, followed by applying an address voltage along the common line to actuate selected electromechanical devices along the common line based on voltages applied along segment lines. Hold voltages may be applied along common lines between applications of release and address voltages, and the segment voltages may be selected to be sufficiently small that the segment voltages will not affect the state of the electromechanical devices along other common lines not being written to.

Claims

1. A method of driving an array of display elements, the method comprising:

applying a voltage waveform to at least a portion of an array of display elements, the voltage waveform comprising a frame write waveform and an hold sequence waveform, wherein a substantial percentage of the frame write waveform has a value substantially equal to a release voltage, a high or low hold voltage, or a high or low address voltage, and wherein a substantial percentage of the hold sequence waveform comprises an adjusted hold voltage substantially different from the high or low hold voltage.

2. The method of claim 1, wherein the adjusted hold voltage is predetermined based on a capacitance of at least one of the display elements.

3. The method of claim 1, wherein the adjusted hold voltage is predetermined so as to provide a desired optical response.

4. The method of claim 1, wherein the adjusted hold voltages is predetermined so as to provide a desired white balance.

5. The method of claim 1, further comprising applying a segment voltage waveform to a crossing portion of the array, the crossing portion of the array at least partially overlapping the portion of the array.

6. The method of claim 5, wherein the segment voltage waveform comprises a segment frame write waveform and a segment hold sequence waveform, wherein a substantial percentage of the segment frame write waveforms comprises a value substantially equal to a high or low segment voltage, wherein a substantial percentage of the segment hold sequence waveform comprises a value substantially equal to an intermediate voltage, and wherein the intermediate voltage is substantially different from the high and low segment voltages.

7. A method of driving an array, the method comprising:

respectively applying a first, second, and third voltage waveform to a first, second, and third portion of an array, wherein each of the first, second, and third voltage waveforms respectively comprises a first, second, and third frame write waveform and a first, second, and third hold sequence waveform, and wherein each of the first, second, and third portions of the array is associated with a different color primary;

wherein a substantial percentage of the first frame write waveform has a value substantially equal to a first release voltage, a first high or low hold voltage, or a first high or low address voltage;

wherein a substantial percentage of the second frame write waveform has a value substantially equal to a second release voltage, a second high or low hold voltage, or a second high or low address voltage;

wherein a substantial percentage of the third frame write waveform has a value substantially equal to a third release voltage, a third high or low hold voltage, or a third high or low address voltage;

wherein a substantial percentage of each of the first, second, and third hold sequence waveforms has a value substantially equal to, respectively, a first, second, and third adjusted hold voltage; and

wherein the first adjusted hold voltage is substantially different from the first high or low hold voltage, the second adjusted hold voltage is substantially different from the second high or low hold voltage, or the third adjusted hold voltage is substantially different from the third high or low hold voltage.

8. The method of claim 7, wherein at least one of the adjusted hold voltages is predetermined so as to provided a desired optical response.

9. The method of claim 8, wherein at least one of the adjusted hold voltages is predetermined so as to provide a desired white balance.

10. The method of claim 8, wherein at least one of the adjusted hold voltages is predetermined such that the color reflected by the first, second, and third portions of the array is at a particular white point.

11. The method of claim 7, wherein the first, second, and third portions of the array are respectively associated with red, green, and blue.

12. The method of claim 7, wherein the frame write waveforms are based at least in part on image update data.

13. The method of claim 7, further comprising applying segment voltage waveforms to a plurality of crossing portions of the array, each crossing portion of the array at least partially overlapping the first, second, and third portion of the array.

14. The method of claim 13, wherein each of the segment voltage waveforms comprise a segment frame write waveform and a segment hold sequence waveform, wherein a substantial percentage of each of the segment frame write waveforms comprises a value substantially equal to a high or low segment voltage, wherein a substantial percentage of each of the segment hold sequence waveforms comprises a value substantially equal to an intermediate voltage, and wherein the intermediate voltage is substantially different from the high and low segment voltages.

15. A system for driving an array, the system comprising:

a circuit configured to generate at least a first, second, and third voltage waveform, wherein each of the first, second, and third voltage waveforms respectively comprises a first, second, and third frame write waveform and a first, second, and third hold sequence waveform,

wherein a substantial percentage of the first frame write waveform has a value substantially equal to a first release voltage, a first high or low hold voltage, or a first high or low address voltage,

wherein a substantial percentage of the second frame write waveform has a value substantially equal to a second release voltage, a second high or low hold voltage, or a second high or low address voltage,

wherein a substantial percentage of the third frame write waveform has a value substantially equal to a third release voltage, a third high or low hold voltage, or a third high or low address voltage,

wherein a substantial percentage of each of the first, second, and third hold sequence waveforms has a value substantially equal to, respectively, a first, second, and third adjusted hold voltage, and

wherein the first adjusted hold voltage is substantially different from the first high or low hold voltage, the second adjusted hold voltage is substantially different from the second high or low hold voltage, or the third adjusted hold voltage is substantially different from the third high or low hold voltage; and

wherein the circuit is further configured to respectively apply the first, second, and third voltage waveforms to a first, second, and third portions of an array, wherein each of the first, second, and third portions of the array is associated with a different color primary.

16. The system of claim 15, wherein the circuit is further configured to receive image data and to generate the first, second, and third voltage waveforms based at least in part on the image data.

17. The system of claim 15, wherein the array is an array of interferometric modulators.

18. A system for driving an array, the system comprising:

means for generating at least a first, second, and third voltage waveform, wherein each of the first, second, and third voltage waveforms respectively comprises a first, second, and third frame write waveform and a first, second, and third hold sequence waveform,

wherein a substantial percentage of the first frame write waveform has a value substantially equal to a first release voltage, a first high or low hold voltage, or a first high or low address voltage,

wherein a substantial percentage of the second frame write waveform has a value substantially equal to a second release voltage, a second high or low hold voltage, or a second high or low address voltage,

wherein a substantial percentage of the third frame write waveform has a value substantially equal to a third release voltage, a third high or low hold voltage, or a third high or low address voltage,

wherein a substantial percentage of each of the first, second, and third hold sequence waveforms has a value substantially equal to, respectively, a first, second, and third adjusted hold voltage, and

wherein the first adjusted hold voltage is substantially different from the first high or low hold voltage, the second adjusted hold voltage is substantially different from the second high or low hold voltage, or the third adjusted hold voltage is substantially different from the third high or low hold voltage; and

means for respectively applying the first, second, and third voltage waveforms to a first, second, and third portions of an array, wherein each of the first, second, and third portions of the array is associated with a different color primary.

19. The system of claim 18, further comprising means for applying segment voltage waveforms to a plurality of crossing portions of the array, each crossing portion of the array at least partially overlapping the first, second, and third portion of the array.

20. The system of claim 19, wherein each of the segment voltage waveforms comprise a segment frame write waveform and an segment hold sequence waveform, wherein a substantial percentage of each of the segment frame write waveforms comprises a value substantially equal to a high or low segment voltage, wherein a substantial percentage of each of the segment hold sequence waveforms comprises a value substantially equal to an intermediate voltage, wherein the intermediate voltage is substantially different from the high and low segment voltages.

21. A computer-readable storage medium comprising instructions which, when executed by one or more processors, causes a computer to perform a method of driving an array, the method comprising:

respectively applying a first, second, and third voltage waveform to a first, second, and third portion of an array, wherein each of the first, second, and third voltage waveforms respectively comprises a first, second, and third frame write waveform and a first, second, and third hold sequence waveform, and wherein each of the first, second, and third portions of the array is associated with a different color primary;

wherein a substantial percentage of the first frame write waveform has a value substantially equal to a first release voltage, a first high or low hold voltage, or a first high or low address voltage;

wherein a substantial percentage of the second frame write waveform has a value substantially equal to a second release voltage, a second high or low hold voltage, or a second high or low address voltage;

wherein a substantial percentage of the third frame write waveform has a value substantially equal to a third release voltage, a third high or low hold voltage, or a third high or low address voltage;

wherein a substantial percentage of each of the first, second, and third hold sequence waveforms has a value substantially equal to, respectively, a first, second, and third adjusted hold voltage; and

wherein the first adjusted hold voltage is substantially different from the first high or low hold voltage, the second adjusted hold voltage is substantially different from the second high or low hold voltage, or the third adjusted hold voltage is substantially different from the third high or low hold voltage.