INTERFACE, MEMORY SYSTEM, AND ACCESS CONTROL METHOD

• US 20100250872A1
• Filed: 01/22/2010
• Published: 09/30/2010
• Est. Priority Date: 03/30/2009
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Inventors: Takashima, Satoshi, Miki, Akihiro, OHHASHI, Shinya
• Granted Patent: US 8,255,668 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers

Abstract

An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.

Claims

1. An interface comprising:

a controller that divides a burst access command into a plurality of command cycles, and supplies the plurality of command cycles to a storage device including a plurality of blocks; and

a block address converter that outputs an address at a first command cycle of the plurality of command cycles, the outputted address being obtained by shifting at least one bit of an external block address input in response to the burst access command,

wherein the outputted address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at one of the plurality of command cycles other than the first command cycle.

2. The interface according to claim 1, wherein the plurality of command cycles are issued consecutively within a period of a burst access.

3. The interface according to claim 2, wherein the plurality of command cycles includes two command cycles.

4. The interface according to claim 1, wherein the block address converter shifts the external block address in response to an identification address identifying data transferred in response to the burst access command.

5. The interface according to claim 4, wherein the identification address is input in response to the burst access command and set based on an initial identification address corresponding to data transferred at the first command cycle.

6. The interface according to claim 4, wherein a data area accessed within a block on an external block address basis is unique.

7. The interface according to claim 6, further comprising

a bus selector that selects a position of a data line to be used in an input-output bus on an external block address basis when a bit width of data transferred at a command cycle is smaller than a bit width of an input-output bus of the storage device.

8. A memory system, comprising:

a storage device which includes a plurality of blocks;

a controller that divides a burst access command into a plurality of command cycles, and supplies the plurality of command cycles to the storage device; and

a block address converter that outputs an address at a first command cycle of the plurality of command cycles, the outputted address being obtained by shifting at least one bit of an external block address input in response to the burst access command,

wherein the outputted address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at one of the plurality of command cycles other than the first command cycle.

9. An access control method, comprising:

dividing a burst access command into a plurality of command cycles; and

supplying the command cycles to a storage device including a plurality of blocks;

supplying an address to the storage device at a first command cycle of the plurality of command cycles, the address being obtained by shifting at least one bit of an external block address input in response to the burst access command; and

supplying the external block address to the storage device at one of the plurality of command cycles other than the first command cycle.