SEMICONDUCTOR NANOWIRE WITH BUILT-IN STRESS

• US 20100252801A1
• Filed: 04/03/2009
• Published: 10/07/2010
• Est. Priority Date: 04/03/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sekaric, Lidija, Chidambarrao, Dureseti, Liu, Xiao H.
• Granted Patent: US 7,902,541 B2
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Claims

1. A semiconductor structure comprising:

a semiconductor nanowire adjoined to a first semiconductor pad and a second semiconductor pad, wherein a middle portion of said semiconductor wire is longitudinally strained;

a gate dielectric surrounding said longitudinally strained middle portion of said semiconductor nanowire; and

a dielectric material layer embedding said first and second semiconductor pads, wherein said dielectric material layer is substantially stress-free.

2. The semiconductor structure of claim 1, further comprising a gate electrode comprising a conductive material and surrounding said gate dielectric.

3. The semiconductor structure of claim 2, further comprising an insulator layer that includes a first dielectric pedestal and a second dielectric pedestal and underlying said semiconductor nanowire, wherein said first dielectric pedestal adjoins said first semiconductor pad, said second dielectric pedestal adjoins said second semiconductor pad, and said gate electrode adjoins said insulator layer.

4. The semiconductor structure of claim 1, further comprising:

a channel region located at said middle portion of said semiconductor wire;

a source region that includes said first semiconductor pad and adjoins said channel region; and

a drain region that includes said second semiconductor pad and adjoins said channel region.

5. The semiconductor structure of claim 4, wherein said source region includes a pad source portion located in said first semiconductor pad and a nanowire source portion located in said semiconductor nanowire, and wherein said drain region includes a pad drain portion located in said second semiconductor pad and a nanowire drain portion located in said semiconductor nanowire.

6. The semiconductor structure of claim 4, wherein a boundary between said source region and said channel region is substantially vertically coincident with an edge of a gate electrode overlying said semiconductor nanowire, and wherein a boundary between said drain region and said channel region is substantially vertically coincident with another edge of said gate electrode

7. The semiconductor structure of claim 4, wherein said channel region has a doping of a first conductivity type, wherein said source region and said drain region have a doping of a second conductivity type, and wherein said second conductivity type is the opposite of said first conductivity type.

8. The semiconductor structure of claim 1, further comprising at least one source-side contact via embedded in said dielectric material layer and contacting said first semiconductor pad and at least one drain-side contact via embedded in said dielectric material layer and contacting said second semiconductor pad.

9. The semiconductor structure of claim 8, wherein a top surface of said dielectric material layer is substantially coplanar with a top surface of said at least one first contact via and a top surface of said at least one second contact via.

10. The semiconductor structure of claim 8, further comprising an insulator layer that includes a first dielectric pedestal and a second dielectric pedestal and underlying said semiconductor nanowire, wherein said first dielectric pedestal adjoins said first semiconductor pad, and said second dielectric pedestal adjoins said second semiconductor pad.

11. The semiconductor structure of claim 10, wherein a portion of said dielectric material layer underlies a portion of said semiconductor nanowire, overlies a portion of said insulator layer, and adjoins a gate electrode and one of said first dielectric pedestal and said second dielectric pedestal.

12. The semiconductor structure of claim 10, wherein said dielectric material layer, said at least one source-side contact via, and said first dielectric pedestal encapsulate said first semiconductor pad, and wherein said dielectric material layer, said at least one drain-side contact via, and said second dielectric pedestal encapsulate said second semiconductor pad.

13. The semiconductor structure of claim 1, wherein said longitudinally strained middle portion of said semiconductor wire has an inherent compressive stress having a magnitude greater than 0.3 GPa.

14. The semiconductor structure of claim 1, wherein said longitudinally strained middle portion of said semiconductor wire has an inherent tensile stress having a magnitude greater than 0.3 GPa.

15. The semiconductor structure of claim 1, wherein said semiconductor nanowire, said first semiconductor pad, and said second semiconductor pad comprise a single crystalline semiconductor material.

16. The semiconductor structure of claim 1, wherein said semiconductor nanowire has a lateral width from 1 nm to 20 nm.

17. A method of forming a semiconductor structure comprising:

forming a semiconductor nanowire on a substrate, wherein said semiconductor nanowire is adjoined to a first semiconductor pad and a second semiconductor pad, and wherein said semiconductor nanowire is suspended over said substrate;

inducing longitudinal strain in a middle portion of said semiconductor nanowire by forming a first stress-generating material portion on said first semiconductor pad and a second stress-generating material portion on said second semiconductor pad;

forming a gate dielectric directly on said middle portion of said semiconductor nanowire while said middle portion is under said longitudinal strain; and

removing said first stress-generating material portion and said second stress-generating material portion, wherein said middle portion of said semiconductor nanowire is longitudinally strained after removal of said first stress-generating material portion and said second stress-generating material portion.

18. The method of claim 17, further comprising:

depositing a stress-generating material layer on said semiconductor nanowire, said first semiconductor pad, and said second semiconductor pad; and

patterning said stress-generating material layer, wherein said first stress-generating material portion and said second stress-generating material portion are formed by remaining portions of said stress-generating dielectric material layer.

19. The method of claim 17, further comprising forming a gate electrode on said gate dielectric.

20. The method of claim 19, wherein said semiconductor nanowire has a doping of a first conductivity type, wherein said method further comprises implanting dopants of a second conductivity type into said first semiconductor pad and said second semiconductor pad, and wherein said second conductivity type is the opposite of said first conductivity type.

21. The method of claim 19, further comprising forming a source region and a drain region, wherein an edge of said source region is located in said semiconductor nanowire and is substantially vertically coincident with an edge of said gate electrode, and an edge of said drain region is substantially vertically coincident with another edge of said gate electrode.

22. The method of claim 17, further comprising:

patterning a top semiconductor layer into a semiconductor link portion over an insulator layer, wherein said semiconductor link portion adjoins said first semiconductor pad and said second semiconductor pad; and

etching said insulator layer underneath said semiconductor link portion, whereby said semiconductor link portion is suspended over said insulator layer.

23. The method of claim 22, further comprising forming a first dielectric pedestal and a second dielectric pedestal by patterning said insulator layer, wherein said first dielectric pedestal adjoins said first semiconductor pad, and wherein said second dielectric pedestal adjoins said second semiconductor pad.

24. The method of claim 23, further comprising:

oxidizing outer portions of said first semiconductor pad, said second semiconductor pad, and said semiconductor link portion; and

removing oxidized portions of said first semiconductor pad, said second semiconductor pad, and said semiconductor link portion, wherein said first semiconductor pad and said second semiconductor pad are reduced in size, and wherein a remaining portion of said semiconductor link portion constitutes said semiconductor nanowire.

25. The method of claim 24, wherein said semiconductor nanowire has a lateral width from 1 nm to 20 nm.