DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20100252826A1
• Filed: 09/30/2009
• Published: 10/07/2010
• Est. Priority Date: 10/03/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AKIMOTO, Kengo, YAMAZAKI, Shunpei, UMEZAKI, Atsushi
• Granted Patent: US 8,344,372 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. The increase in the numbers of gate lines and signal lines makes it difficult to mount an IC chip having a driver circuit for driving the gate line and the signal line by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit driving the pixel portion are provided over the same substrate. The pixel portion and at least a part of the driver circuit are formed using thin film transistors in each of which an oxide semiconductor is used. Both the pixel portion and the driver circuit are provided over the same substrate, whereby manufacturing costs are reduced.

Claims

1. A display device comprising:

a pixel portion comprising a first thin film transistor including a first oxide semiconductor layer; and

a driver circuit comprising a second thin film transistor including a second oxide semiconductor layer and a third thin film transistor including a third oxide semiconductor layer, the second thin film transistor including a gate electrode below the second oxide semiconductor layer,

wherein a wiring is directly connected to the gate electrode of the second thin film transistor, and

wherein the third oxide semiconductor layer is directly connected to the wiring.

2. The display device according to claim 1, wherein the wiring is electrically connected to the gate electrode of the second thin film transistor through a contact hole formed in a gate insulating layer.

3. The display device according to claim 1, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer contain indium, gallium, and zinc.

4. The display device according to claim 1, wherein the pixel portion and the driver circuit are provided over the same substrate.

5. A display device comprising:

a pixel portion over a substrate, the pixel portion comprising;

a first thin film transistor including a first gate electrode and a first oxide semiconductor layer over the first gate electrode with a gate insulating layer between the first gate electrode and the first oxide semiconductor layer; and

a driver circuit over the substrate, the driver circuit comprising;

a wiring over the gate insulating layer; and

a second thin film transistor including a second gate electrode and a second oxide semiconductor layer over the second gate electrode with the gate insulating layer between the second gate electrode and the second oxide semiconductor layer, wherein the second oxide semiconductor layer overlaps the wiring,

wherein the wiring is in contact with the second oxide semiconductor layer and the second gate electrode.

6. The display device according to claim 5, wherein the wiring is in contact with the second gate electrode through a contact hole formed in the gate insulating layer.

7. The display device according to claim 5, wherein the first oxide semiconductor layer and the second oxide semiconductor layer contain indium, gallium, and zinc.

8. A display device comprising:

a pixel portion over a substrate, the pixel portion comprising;

a first thin film transistor including a first gate electrode and a first oxide semiconductor layer over the first gate electrode with a gate insulating layer between the first gate electrode and the first oxide semiconductor layer; and

a driver circuit over the substrate, the driver circuit comprising;

a wiring over the gate insulating layer;

a second thin film transistor including a second gate electrode and a second oxide semiconductor layer over the second gate electrode with the gate insulating layer between the second gate electrode and the second oxide semiconductor layer, wherein the second oxide semiconductor layer overlaps the wiring; and

a third thin film transistor including a third gate electrode and a third oxide semiconductor layer over the third gate electrode with the gate insulating layer between the third gate electrode and the third oxide semiconductor layer, wherein the third oxide semiconductor layer overlaps the wiring,

wherein the wiring is in contact with the second oxide semiconductor layer, the third oxide semiconductor layer, and the third gate electrode.

9. The display device according to claim 8, wherein the wiring is in contact with the third gate electrode through a contact hole formed in the gate insulating layer.

10. The display device according to claim 8, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer contain indium, gallium, and zinc.

11. A method for manufacturing a display device, comprising the steps of:

forming a first gate electrode and a second gate electrode over a substrate;

forming a gate insulating layer over the first gate electrode and the second gate electrode;

forming a contact hole in the gate insulating layer;

forming a first wiring directly connected to the second gate electrode through the contact hole and a second wiring overlapping with both the first gate electrode and the second gate electrode with the first gate insulating layer interposed therebetween; and

forming a first oxide semiconductor layer overlapping with the first gate electrode over the gate insulating layer and the second wiring and a second oxide semiconductor layer overlapping with the first gate electrode over the gate insulating layer, the first wiring and the second wiring,

wherein the second oxide semiconductor layer is in direct contact with the first wiring and the second wiring.

12. The method for manufacturing a display device according to claim 11, wherein plasma treatment is performed on a surface of the gate insulating layer before the first oxide semiconductor layer and the second oxide semiconductor layer are formed.

13. The method for manufacturing a display device according to claim 11, wherein plasma treatment is performed on a surface of the gate insulating layer and a bottom surface of the contact hole before the first wiring and the second wiring are formed.