Package-on-package interconnect stiffener

• US 20100258927A1
• Filed: 04/10/2009
• Published: 10/14/2010
• Est. Priority Date: 04/10/2009
• Status: Active Grant

• Current Assignee: Intel Corporation, Intel Limited (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Arane, Leonel R., Kanaoka, Yosuke, Viswanath, Ram S., Ganesan, Sanka, Tomita, Yoshihiro, Swaminathan, Rajasekaran, Guzek, John S., Nickerson, Robert M.
• Granted Patent: US 8,513,792 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/488 consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

Claims

1. A semiconductor assembly, comprising:

a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; and

a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener configured to electrically connect a second semiconductor package, and a second plurality of planar contact pads on the bottom side of the stiffener electrically connected to the inter-package contact pads of the first package.

2. The assembly of claim 1, wherein the stiffener comprises:

a substrate having a through recess adapted to house a die attached to the first package, and a plurality of through openings throughwhich the first and second pluralities of contact pads are disposed;

a solder-wettable planar surface finish on the first and second pluralities of contact pads; and

a conductive trace electrically interconnecting the first plurality of contact pads to the corresponding second plurality of contact pads.

3. The assembly of claim 2, wherein the stiffener includes an adhesive of low glass transition temperature (T_g) attaching the bottom side of the substrate to the first package.

4. The assembly of claim 1, wherein the stiffener includes routing features accommodating various circuitry designs of the second package.

5. The assembly of claim 1, wherein the second plurality of contact pads of the stiffener is connected to the first package by way of conductive micro balls.

6. The assembly of claim 2, wherein the substrate includes a coefficient of thermal expansion (CTE) approximately between 15 and 25 ppm, and a flexural modulus approximately between 15 and 30 GPa.

7. The assembly of claim 1, wherein the layout of the second plurality of planar contact pads of the stiffener matches the layout of the inter-package contact pads of the first package.

8. The assembly of claim 1, wherein the stiffener includes a plug material disposed between the first plurality and the second plurality of contact pads.

9. The assembly of claim 2, wherein the stiffener includes a plug material disposed in the substrate of the stiffener.

10. A package-on-package (PoP) assembly, comprising:

a first semiconductor package having a plurality of inter-package contact pads and

a plurality of second level interconnect (SLI) pads;

a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and

a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

11. The assembly of claim 10, wherein the stiffener includes routing features accommodating various circuitry designs of the second package.

12. The assembly of claim 11, wherein the substrate includes a coefficient of thermal expansion (CTE) approximately between 15 and 25 ppm, and a flexural modulus approximately between 15 and 30 GPa.

13. The assembly of claim 10, wherein the layout of the second plurality of planar contact pads of the stiffener matches the layout of the inter-package contact pads of the first package.

14. The assembly of claim 10, wherein the stiffener includes a plug material disposed between the first plurality and the second plurality of planar contact pads.

15. The assembly of claim 10, wherein the stiffener includes a plug material disposed in the substrate.

16. A method to form a package-on-package (PoP) assembly, comprising:

providing a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads;

attaching micro balls to the inter-package contact pads of the first package;

connecting a planar stiffener to the micro balls attached to the first package, the stiffener having a first plurality of planar contact pads on the top side of the stiffener to receive a second semiconductor package, and a second plurality of planar contact pads to connect the stiffener to the micro balls attached to the first package; and

reflowing the micro balls to form electrical connection between the stiffener and the first package.

17. The method of claim 16, further comprising attaching a bottom side of the stiffener to the first package by way of an adhesive of low glass transition temperature (T_g).

18. The method of claim 16, wherein the stiffener comprises:

a substrate having a through recess adapted to house a die attached to the first package, and a plurality of through openings throughwhich the first and second pluralities of contact pads are disposed;

a solder-wettable planar surface finish on the first and second pluralities of contact pads; and

a conductive trace electrically connecting the first plurality of contact pads to the corresponding second plurality of contact pads.