Semiconductor Device and Driving Method Thereof

• US 20100259314A1
• Filed: 06/23/2010
• Published: 10/14/2010
• Est. Priority Date: 02/28/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Shionoiri, Yutaka, Kato, Kiyoshi
• Granted Patent: US 7,876,859 B2
• Time in Patent Office: Days
• US Class Current: 327/520
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components

Abstract

The invention provides a semiconductor device with high yield by reducing an effect of variations in characteristics of a semiconductor element. Further, by reducing an effect of variations in characteristics of a semiconductor element to improve productivity, an inexpensive semiconductor device can be provided. Further, an inexpensive semiconductor device can be provided by forming a semiconductor device in a large amount over a large substrate such as a glass substrate and a flexible substrate. A semiconductor device of the invention includes a demodulation signal generating circuit and an antenna or a wire for connecting the antenna. The demodulation signal generating circuit includes a demodulation circuit and a correction circuit. The correction circuit corrects a first demodulation signal generated from the demodulation circuit and generates a second demodulation signal.

Claims

1-44. -44. (canceled)

45. A management system of an object, the management system comprising:

a reader/writer; and

a semiconductor device which is provided to the object and capable of transmitting and receiving electromagnetic waves to/from the reader/writer,

wherein the semiconductor device comprising;

a resonant circuit for generating an alternating signal;

a power source circuit for rectifying the alternating signal and generating a power source voltage and a ground voltage;

a demodulation circuit for demodulating the alternating signal and generating a first demodulation signal; and

a correction circuit for correcting the first demodulation signal and generating a second demodulation signal,

wherein the first demodulation signal is a digital signal having a Low level potential and a High level potential,

wherein the correction circuit corrects the first demodulation signal when the High level potential of the first demodulation signal becomes lower than the power source voltage or when the Low level potential of the first demodulation signal does not become as low as the ground voltage, and

wherein an amplitude of the second demodulation signal is equal to an amplitude of the power source voltage.

46. The management system according to claim 45,

wherein the resonant circuit, the demodulation circuit, and the correction circuit are formed over a same substrate which is a glass substrate or a flexible substrate.

47. The management system according to claim 45,

wherein the demodulation circuit and the correction circuit are formed over a first substrate,

wherein the resonant circuit is formed over a second substrate, and

wherein each of the first substrate and the second substrate is a glass substrate or a flexible substrate.

48. The management system according to claim 45,

wherein the demodulation circuit comprises a plurality of transistors.

49. The management system according to claim 45,

wherein the correction circuit comprises a plurality of transistors.

50. The management system according to claim 45, further comprising at least one of a clock generating circuit, a memory, a memory control circuit, and a modulation circuit.

51. The management system according to claim 45,

wherein the correction circuit includes an inverter comprising an N-channel transistor and a P-channel transistor, and

wherein the inverter has a voltage level of a changing point of input/output characteristics within a range of 25 to 45% of the power source voltage.

52. The management system according to claim 51,

wherein a channel width of the N-channel transistor is wider than a channel width of the P-channel transistor.

53. The management system according to claim 51,

wherein the channel width of the N-channel transistor is 1 to 10 times as wide as the channel width of the P-channel transistor.

54. The management system according to claim 51,

wherein a channel length of the P-channel transistor is longer than a channel length of the N-channel transistor.

55. The management system according to claim 51,

wherein an absolute value of a threshold voltage of the P-channel transistor is larger than an absolute value of a threshold voltage of the N-channel transistor.

56. The management system according to claim 45,

wherein the correction circuit includes an inverter comprising an N-channel transistor and a P-channel transistor, and

wherein the inverter has a voltage level of a changing point of input/output characteristics within a range of 55 to 75% of the power source voltage.

57. The management system according to claim 56,

wherein a channel width of the P-channel transistor is wider than a channel width of the N-channel transistor.

58. The management system according to claim 57,

wherein the channel width of the P-channel transistor is 4 to 20 times as wide as the channel width of the N-channel transistor.

59. The management system according to claim 56,

wherein a channel length of the N-channel transistor is longer than a channel length of the P-channel transistor.

60. The management system according to claim 56,

wherein an absolute value of a threshold voltage of the N-channel transistor is larger than an absolute value of a threshold voltage of the P-channel transistor.

61. The management system according to claim 45,

wherein the resonant circuit includes an antenna.

62. The management system according to claim 45,

wherein the correction circuit includes a level shifter.

63. The management system according to claim 45,

wherein the correction circuit includes a differential amplifier.

64. The management system according to claim 45,

wherein the object is selected from securities, certificates, bearer bonds, packaging containers, books, memory media, personal belongings, vehicles, groceries, garments, health products, daily commodities, medicals, or electronic devices.

65. A management system of an object, the management system comprising:

a reader/writer; and

a semiconductor device which is provided to the object and capable of transmitting and receiving electromagnetic waves to/from the reader/writer,

wherein the semiconductor device comprising;

an antenna for generating an alternating signal;

a power source circuit for rectifying the alternating signal and generating a power source voltage and a ground voltage;

a demodulation circuit for demodulating the alternating signal and generating a first demodulation signal; and

a correction circuit for correcting the first demodulation signal and generating a second demodulation signal,

wherein the first demodulation signal is a digital signal having a Low level potential and a High level potential,

wherein the correction circuit corrects the first demodulation signal when the High level potential of the first demodulation signal becomes lower than the power source voltage or when the Low level potential of the first demodulation signal does not become as low as the ground voltage, and

wherein an amplitude of the second demodulation signal is equal to an amplitude of the power source voltage.

66. The management system according to claim 65,

wherein the antenna, the demodulation circuit, and the correction circuit are formed over a same substrate which is a glass substrate or a flexible substrate.

67. The management system according to claim 65,

wherein the demodulation circuit and the correction circuit are formed over a first substrate,

wherein the antenna is formed over a second substrate, and

wherein each of the first substrate and the second substrate is a glass substrate or a flexible substrate.

68. The management system according to claim 65,

wherein the demodulation circuit comprises a plurality of transistors.

69. The management system according to claim 65,

wherein the correction circuit comprises a plurality of transistors.

70. The management system according to claim 65, further comprising at least one of a clock generating circuit, a memory, a memory control circuit, and a modulation circuit.

71. The management system according to claim 65,

wherein the correction circuit includes an inverter comprising an N-channel transistor and a P-channel transistor, and

wherein the inverter has a voltage level of a changing point of input/output characteristics within a range of 25 to 45% of the power source voltage.

72. The management system according to claim 71,

wherein a channel width of the N-channel transistor is wider than a channel width of the P-channel transistor.

73. The management system according to claim 71,

wherein the channel width of the N-channel transistor is 1 to 10 times as wide as the channel width of the P-channel transistor.

74. The management system according to claim 71,

wherein a channel length of the P-channel transistor is longer than a channel length of the N-channel transistor.

75. The management system according to claim 71,

wherein an absolute value of a threshold voltage of the P-channel transistor is larger than an absolute value of a threshold voltage of the N-channel transistor.

76. The management system according to claim 65,

wherein the correction circuit includes an inverter comprising an N-channel transistor and a P-channel transistor, and

wherein the inverter has a voltage level of a changing point of input/output characteristics within a range of 55 to 75% of the power source voltage.

77. The management system according to claim 76,

wherein a channel width of the P-channel transistor is wider than a channel width of the N-channel transistor.

78. The management system according to claim 77,

wherein the channel width of the P-channel transistor is 4 to 20 times as wide as the channel width of the N-channel transistor.

79. The management system according to claim 76,

wherein a channel length of the N-channel transistor is longer than a channel length of the P-channel transistor.

80. The management system according to claim 76,

wherein an absolute value of a threshold voltage of the N-channel transistor is larger than an absolute value of a threshold voltage of the P-channel transistor.

81. The management system according to claim 65,

wherein the correction circuit includes a level shifter.

82. The management system according to claim 65,

wherein the correction circuit includes a differential amplifier.

83. The management system according to claim 65,

wherein the object is selected from securities, certificates, bearer bonds, packaging containers, books, memory media, personal belongings, vehicles, groceries, garments, health products, daily commodities, medicals, or electronic devices.