IMAGE SENSOR WITH GLOBAL SHUTTER

• US 20100276574A1
• Filed: 04/30/2009
• Published: 11/04/2010
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Manabe, Sohei
• Granted Patent: US 8,089,036 B2
• Time in Patent Office: Days
• US Class Current: 250/214A
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

An image sensor includes a photodiode to accumulate an image charge and a storage transistor to store the image charge. A transfer transistor is coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor. An output transistor is coupled to an output of the storage transistor to selectively transfer the image charge to a readout node and a reset transistor is coupled to the readout node. A controller is configured to apply a negative voltage to a gate of the storage transistor before activating the gate of the storage transistor to store the image charge.

Claims

1. An apparatus, comprising:

a photodiode to accumulate an image charge;

a storage transistor to store the image charge;

a transfer transistor coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor;

an output transistor coupled to an output of the storage transistor to selectively transfer the image charge to a readout node;

a reset transistor coupled to the readout node; and

a controller configured to apply a negative voltage to a gate of the storage transistor before activating the gate of the storage transistor to store the image charge.

2. The apparatus of claim 1, wherein the negative voltage is at least 0.5 volts below a threshold voltage of the storage transistor.

3. The apparatus of claim 1, wherein the negative voltage is approximately −

1.2 volts.

4. The apparatus of claim 1, further comprising a first select transistor coupled between the transfer transistor and the storage transistor to selectively transfer the image charge from the transfer transistor to the storage transistor.

5. The apparatus of claim 4, further comprising a second select transistor coupled between the readout node and a circuit node between the transfer transistor and the first select transistor, the controller further configured to reset the photodiode by activating the transfer transistor, the second select transistor, and the reset transistor.

6. The apparatus of claim 5, wherein the readout node comprises a doped floating diffusion.

7. The apparatus of claim 5, wherein the transfer transistor is larger than each of the first and second select transistors, the output transistor, and the reset transistor.

8. The apparatus of claim 5, wherein the transfer transistor, the first select transistor, the second select transistor, the storage transistor, and the output transistor are directly interconnected by their channels and operate collectively as a charged coupled device.

9. The apparatus of claim 1, further comprising:

an amplifier transistor having a gate coupled to the readout node; and

a row select transistor coupled between a bitline and the amplifier transistor.

10. The apparatus of claim 1, wherein the storage transistor has a buried channel.

11. The apparatus of claim 1, wherein the storage transistor has a surface channel.

12. A method of operation of a pixel array, the method comprising:

resetting a photodiode within each pixel of the pixel array prior to accumulating an image charge;

negatively biasing a gate of a storage transistor within each of the pixels while the storage transistor is off and prior to temporarily storing the image charge within the storage transistor;

asserting a global shutter signal to transfer the image charge accumulated by the photodiode of each pixel to the storage transistor of each pixel; and

storing the image charge within the storage transistor of each pixel until the image charge is readout.

13. The method of claim 12, wherein negatively biasing the gate comprises biasing the gate at least 0.5 volts below a threshold voltage of the storage transistor.

14. The method of claim 12, wherein resetting the photodiode and asserting the global shutter signal to transfer the image charge both comprise activating a transfer transistor coupled between the photodiode and the storage transistor.

15. The method of claim 14, wherein resetting the photodiode of each pixel comprises contemporaneously pre-charging the photodiode of each pixel within the pixel array.

16. The method of claim 15, wherein:

a first portion of the storage transistors whose image charge has already been readout for a given imaging cycle are off while resetting the photodiode of each pixel, and

a second portion of the storage transistors whose image charge has not already been readout for the given imaging cycle are on while resetting the photodiode of each pixel.

17. The method of claim 14, wherein resetting the photodiode within each pixel of the pixel array prior to accumulating the image charge comprises:

deactivating the a first select transistor coupled between the transfer transistor and the storage transistor;

activating a reset transistor of each pixel; and

activating a second select transistor coupled between the reset transistor and a circuit node disposed between the transfer transistor and the first select transistor.

18. The method of claim 12, wherein the image charge of each pixel is readout using a row-by-row readout of the pixel array and wherein negatively biasing the gate of the storage transistor within each of the pixels while the storage transistor is off reduces leakage current.

19. An imaging system comprising:

an array of imaging pixels having the imaging pixels arranged in rows and columns, wherein each imaging pixel includes;

a photodiode to accumulate an image charge;

a storage transistor to store the image charge;

a transfer transistor coupled between the photodiode and the storage transistor;

a first select transistor coupled between the transfer transistor and an input of the storage transistor;

an output transistor coupled to an output of the storage transistor and a readout node;

a reset transistor coupled between a voltage rail and the readout node; and

a second select transistor coupled between the readout node and a circuit node between the transfer transistor and the first select transistor; and

control circuitry coupled to the array of imaging pixels to control timing operation of the storage transistor, the transfer transistor, the first select transistor, the output transistor, the reset transistor, and the second select transistor.

20. The imaging system of claim 19, wherein the control circuit is configured to apply a negative bias voltage to a gate storage transistor being at least 0.5 volts below a threshold voltage of the storage transistor while the storage transistor is turned off to reduce leakage current.

21. The imaging system of claim 19, wherein the transfer transistor, the first select transistor, the second select transistor, the storage transistor, and the output transistor are directly interconnected by their channels and operate collectively as a charged coupled device.

22. The imaging system of claim 19, wherein the control circuit is configured to operate the transfer transistor to reset the photodiode through the second select transistor and to operate the transfer transistor as an image shutter to commence transfer of the image charge to the storage transistor through the first select transistor.