Wafer Backside Structures Having Copper Pillars

• US 20100276787A1
• Filed: 02/18/2010
• Published: 11/04/2010
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Hsu, Kuo-Ching, Chen, Chen-Shien, Huang, Hon-Lin
• Granted Patent: US 8,759,949 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13171 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/13172 : Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13583 : Three-layer coating
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate comprising a front side and a backside;

a conductive via penetrating the semiconductor substrate, the conductive via comprising a back end extending to the backside of the semiconductor substrate;

a redistribution line (RDL) on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via;

a passivation layer over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening; and

a copper pillar having a portion in the opening and electrically connected to the RDL.

2. The integrated circuit structure of claim 1, wherein the RDL comprises:

an RDL strip comprising a portion directly over, and contacting, the conductive via; and

an RDL pad having a greater width than the RDL strip, wherein the copper pillar comprises a bottom surface contacting a top surface of the RDL pad.

3. The integrated circuit structure of claim 1 further comprising:

a barrier layer directly over the copper pillar; and

a solder layer directly over the barrier layer, wherein sidewalls of the copper pillar, the barrier layer, and the solder layer are substantially vertically aligned.

4. The integrated circuit structure of claim 1 further comprising a metal finish on a top surface and sidewalls of the copper pillar, wherein the metal finish comprises a metal selected from the group consisting essentially of nickel, gold, palladium, and combinations thereof.

5. The integrated circuit structure of claim 1, wherein the copper pillar has a height greater than about 15 μ

m.

6. The integrated circuit structure of claim 1, wherein the copper pillar comprises a top surface higher than a top surface of the passivation layer.

7. The integrated circuit structure of claim 1, wherein the conductive via extends from the backside of the semiconductor substrate to the front side of the semiconductor substrate.

8. An integrated circuit structure comprising:

a semiconductor substrate comprising a front side and a backside;

a conductive via extending from the backside of the semiconductor substrate into the semiconductor substrate, wherein a back end of the conductive via is exposed through the backside of the semiconductor substrate;

a redistribution line (RDL) over the backside of the semiconductor substrate and connected to the back end of the conductive via, the RDL comprising;

an RDL strip contacting the conductive via; and

an RDL pad having a greater width than the RDL strip, wherein the RDL pad joins the RDL strip;

a passivation layer over the RDL;

an opening in the passivation layer, wherein a middle portion of the RDL pad is exposed through the opening, and wherein edge portions of the RDL pad are covered by the passivation layer; and

a copper pillar in the opening and contacting the middle portion of the RDL.

9. The integrated circuit structure of claim 8, wherein the copper pillar has a thickness greater than about 15 μ

m.

10. The integrated circuit structure of claim 8 further comprising a nickel layer over and contacting the copper pillar.

11. The integrated circuit structure of claim 10 further comprising a solder layer directly over the nickel layer, and wherein the solder layer and the nickel layer are substantially limited to a region directly over the copper pillar.

12. The integrated circuit structure of claim 10, wherein the nickel layer comprises a portion directly over the copper pillar, and wherein the integrated circuit structure further comprises a gold layer over the nickel layer.

13. The integrated circuit structure of claim 10, wherein the nickel layer comprises a portion directly over the copper pillar, and wherein the integrated circuit structure further comprising a palladium layer over the nickel layer.

14. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate comprising a front side and a backside;

providing a conductive via penetrating the semiconductor substrate, the conductive via comprising a back end extending to the backside of the semiconductor substrate;

forming a redistribution line (RDL) on the backside of the semiconductor substrate and connected to the back end of the conductive via;

forming a passivation layer over the RDL;

forming an opening in the passivation layer, with a portion of the RDL being exposed through the opening; and

forming a copper pillar having a portion in the opening, wherein the copper pillar is electrically connected to, and over, the RDL.

15. The method of claim 14, wherein the step of forming the copper pillar comprises electro plating.

16. The method of claim 15 further comprising:

forming a photo resist over the passivation layer, wherein the photo resist is filled into the opening;

before the step of forming the copper pillar, patterning the photo resist so that the opening in the passivation layer is exposed through the photo resist;

after the step of forming the copper pillar, electro plating a barrier layer on the copper pillar;

plating a solder layer on the barrier layer; and

removing the photo resist after the step of plating the solder layer.

17. The method of claim 15 further comprising:

before the step of forming the copper pillar, forming a photo resist over the passivation layer, wherein the photo resist is filled into the opening;

before the step of forming the copper pillar, patterning the photo resist so that the opening in the passivation layer is exposed through the photo resist;

after the step of forming the copper pillar, removing the photo resist;

after the step of removing the photo resist, forming a metal finish on a top surface and sidewalls of the copper pillar.

18. The method of claim 14, wherein the copper pillar has a height greater than about 15 μ

m.

19. The method of claim 14, wherein the RDL comprises copper.