Method and Mechanism to Reduce Current Variation in a Current Reference Branch Circuit

• US 20100289563A1
• Filed: 05/14/2009
• Published: 11/18/2010
• Est. Priority Date: 05/14/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Katz, Oded, Wagner, Israel A.
• Granted Patent: US 7,994,846 B2
• Time in Patent Office: Days
• US Class Current: 327/543
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A novel and useful system and method of providing a feedback mechanism to reduce current variation observed in a current reference branch circuit by using body voltage control to compensate process, temperature and supply voltage variations. The current reference output voltage, which is proportional to the reference current, is sampled into a feedback loop, which controls the field effect transistor body voltage. The method and mechanism of the present invention uses Corner Robust Current Reference in order to keep the design simple and diminish variation between Process Voltage Temperature (PVT) corners. This method exhibits superior robustness with smaller variation in the reference current magnitude.

Claims

1. A current reference branch circuit, comprising:

a main reference branch sub-circuit operative to supply a reference voltage to current source branches; and

an amplifier operative to reduce output voltage variation of said main reference branch sub-circuit.

2. The circuit according to claim 1, wherein said main reference branch sub-circuit comprises:

a metal oxide semiconductor (MOS) transistor; and

a second device connected to the drain terminal and the gate terminal of said MOS transistor via a diode connection.

3. The circuit according to claim 2, wherein said second device is chosen from the group consisting of an MOS transistor and a resistor.

4. The circuit according to claim 1, wherein said amplifier is chosen from the group consisting of an operational amplifier and a differential amplifier.

5. The circuit according to claim 2, wherein voltage sampled at said diode connection comprises an input to said amplifier.

6. The circuit according to claim 2, wherein output of said amplifier is connected to the bulk terminal of said MOS transistor.

7. The circuit according to claim 1, wherein apparatus for implementation of said current reference branch circuit is chosen from the group consisting of silicon on insulator technology and bulk technology with double well and triple well MOS devices.

8. A current reference branch circuit, comprising:

a main branch sub-circuit operative to supply a first reference voltage to current source branches; and

a replica branch sub-circuit operative to reduce output voltage variation of said main branch sub-circuit.

9. The circuit according to claim 8, wherein said main branch sub-circuit comprises:

a first metal oxide semiconductor (MOS) transistor; and

a second device connected to the drain terminal and the gate terminal of said MOS transistor via a first diode connection.

10. The circuit according to claim 9, wherein said second device is chosen from the group consisting of an MOS transistor and a resistor.

11. The circuit according to claim 8, wherein said replica branch sub-circuit comprises:

a third metal oxide semiconductor (MOS) transistor;

a fourth device connected to the drain terminal and the gate terminal of said MOS transistor via a second diode connection; and

an amplifier, wherein voltage sampled at said second diode comprises an input to said amplifier.

12. The circuit according to claim 11, wherein said fourth device is chosen from the group consisting of an MOS transistor and a resistor.

13. The circuit according to claim 11, wherein said amplifier is chosen from the group consisting of an operational amplifier and a differential amplifier.

14. The circuit according to claim 11, wherein output of said amplifier is connected to the bulk port of said first MOS transistor.

15. The circuit according to claim 8, wherein apparatus for implementation of said current reference branch circuit is chosen from the group consisting of silicon on insulator technology and bulk technology with double well and triple well MOS devices.

16. A method of reducing current variation in a current reference branch circuit, said current reference branch circuit comprising a metal oxide semiconductor (MOS) transistor connected to a second device via a diode connection, the method comprising the steps of:

sampling a reference voltage at the gate terminal of said MOS transistor;

first feeding said sampled voltage to an input terminal of an amplifier; and

second feeding the output terminal of said amplifier to the bulk terminal of said MOS transistor.

17. The method according to claim 16, wherein said device is chosen from the group consisting of an MOS transistor and a resistor.

18. The method according to claim 16, wherein said diode connection couples the drain terminal of said MOS transistor to both a terminal of said second device and the gate terminal of said MOS transistor.

19. The method according to claim 16, wherein said amplifier is chosen from the group consisting of an operational amplifier and a differential amplifier.

20. A method of reducing current variation in a current reference branch circuit, said current reference branch circuit comprising a first metal oxide semiconductor (MOS) transistor connected to a terminal of a second device via a diode connection, the method comprising the steps of:

creating a replica reference branch of said current reference branch circuit;

first feeding the reference voltage from said replica reference branch to the input of an amplifier; and

second feeding the output signal of said amplifier to the bulk terminal of said first MOS transistor.

21. The method according to claim 20, wherein said second device is chosen from the group consisting of an MOS transistor and a resistor.

22. The method according to claim 20, wherein said amplifier is chosen from the group consisting of an operational amplifier and a differential amplifier.

23. The method according to claim 20, wherein said replica reference branch comprises:

a third metal oxide semiconductor (MOS) transistor; and

a fourth device connected to the drain terminal and the gate terminal of said first device via a diode connection.

24. The method according to claim 21, wherein said fourth device is chosen from the group consisting of an MOS transistor and a resistor.

25. The method according to claim 21, wherein said step of first feeding comprises coupling said diode connection of said replica reference branch to said amplifier.