FIELD EFFECT TRANSISTOR FABRICATION FROM CARBON NANOTUBES

• US 20100295023A1
• Filed: 04/06/2010
• Published: 11/25/2010
• Est. Priority Date: 04/06/2009
• Status: Active Grant

• Current Assignee: Purdue Research Foundation (The Trustees of Purdue University (d/b/a Purdue University))
• Original Assignee: Purdue Research Foundation (The Trustees of Purdue University (d/b/a Purdue University))
• Inventors: Franklin, Aaron D., Sands, Timothy D., Fisher, Timothy S., Janes, David B.
• Granted Patent: US 8,872,154 B2
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/491 Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
• CPC Class Codes: H10K 85/221 Carbon nanotubes

Abstract

Methods and apparatus for an electronic device such as a field effect transistor. One embodiment includes fabrication of an FET utilizing single walled carbon nanotubes as the semiconducting material. In one embodiment, the FETs are vertical arrangements of SWCNTs, and in some embodiments prepared within porous anodic alumina (PAA). Various embodiments pertain to different methods for fabricating the drains, sources, and gates.

Claims

1. A field effect transistor, comprising:

an insulating material defining a pore, the pore including a catalyst for growing a carbon nanotube;

a semiconducting carbon nanotube grown from the catalyst within the pore, the nanotube having two ends;

a drain in electrical communication with one end of said nanotube;

a source in electrical communication with the other end of said nanotube; and

a gate surrounding a portion of said nanotube intermediate of the two ends.

2. The field effect transistor of claim 1 wherein the insulating material is aluminum oxide.

3. The field effect transistor wherein of claim 1 the insulating material is a first insulating material, which further comprises a second insulating material substantially surrounding said nanotube within the pore.

4. The field effect transistor of claim 3 wherein the second insulating material is a glass.

5. The field effect transistor of claim 1 which further comprises a nanowire within the pore electrically connecting said one end of said nanotube to said drain.

6. The field effect transistor of claim 1 which further comprises a nanowire within the pore electrically connecting said other end of said nanotube to said source.

7. A method for fabricating an electronic device, comprising:

providing a porous template of an electrically insulating material, each pore including at least one vertically oriented carbon nanotube;

establishing a common electrical connection among one end of each carbon nanotube;

placing a first dielectric material in each pore of the template;

removing a portion of the insulating material and exposing a portion of the first dielectric material;

placing a conducting material around the exposed portions of the first dielectric material; and

surrounding the conducting material with a second dielectric material.

8. The method of claim 7 which further comprises removing a top portion of the device sufficient to provide electrical access to each nanotube.

9. The method of claim 8 which further comprises placing a second conducting material on the top of the device, the second conducting material being in electrical communication with at least one nanotube.

10. The method of claim 9 wherein the device is a field effect transistor and the second conducting material is one of the source or drain.

11. The method of claim 10 wherein the device is a field effect transistor and the common electrical connection is the other of the source or the drain.

12. The method of claim 7 wherein the device is a field effect transistor and the common electrical connection is one of the source or the drain.

13. The method of claim 7 wherein the first dielectric material is the same as the second dielectric material.

14. The method of claim 7 wherein said placing is by spinning on a glass.

15. The method of claim 7 wherein said surrounding is by atomic layer deposition.

16. The method of claim 7 wherein the porous template comprises porous anodic alumina.

17. The method of claim 7 wherein said providing includes a nanotube grown within each pore.

18. The method of claim 7 wherein the common electrical connection includes a metallic planar layer proximate to the closed end of each pore.

19. The method of claim 7 wherein the common electrical connection includes an electrically conductive material deposited in the bottom of each pore.

20. The method of claim 19 wherein the material deposited in each pore is a palladium nanowire.

21. A method for fabricating an electronic device, comprising:

providing an electrically insulating substrate;

placing a pattern of electrodes on the substrate;

depositing an electrically insulating material on at least a portion of the electrodes;

removing a portion of the deposited insulating material and exposing an area of an electrode;

depositing aluminum within the exposed area; and

anodizing the deposited aluminum and creating a plurality of vertical pores.

22. The method of claim 21 wherein said placing a pattern is by lithography

23. The method of claim 22 wherein said placing a pattern include depositing of a material chosen from the group of titanium and platinum.

24. The method of claim 23 wherein said depositing is by electron beam evaporation.

25. The method of claim 21 wherein said removing includes lithographically patterning the deposited insulating material.

26. The method of claim 21 which further comprises etching the deposited insulating material after said removing.

27. The method of claim 26 wherein said etching is a wet buffered oxide etch.

28. The method of claim 26 wherein said etching is a reactive ion etch.

29. The method of claim 21 which further comprises depositing within the exposed area a catalyst for growing carbon nanotubes.

30. The method of claim 29 which further comprises growing carbon nanotubes within at least one pore.

30-1. A method for fabricating an electronic device, comprising:

providing a first insulating material having a porous array, each pore including a nanotube, each pore having an end proximate to a conductive layer

placing the insulating material next to a dielectric material;

depositing a first conductive material within each pore and establishing electrical communication between the nanotube and the conductive layer;

depositing a second insulating material on at least a portion of the deposited first conductive material; and

depositing a second conductive material on at least a portion of the deposited second insulating material.

32. The method of claim 31 wherein the first conductive material includes palladium.

33. The method of claim 31 wherein the conductive layer includes titanium.

34. The method of claim 31 wherein the porous array is anodized alumina.

35. The method of claim 31 wherein the second conductive material includes aluminum.

36. The method of claim 31 wherein said depositing a second insulating material is by atomic layer deposition.

37. The method of claim 31 wherein the second insulating material in alumina.

38. The method of claim 31 wherein the device is a field effect transistor, each nanotube is surrounded by a gate, and the second conductive material provides electrical communication among the gates.

39. A method for fabricating an electronic device, comprising:

providing a substrate comprising an insulating material;

depositing a first layer of a first conductive material on the substrate;

depositing a second layer of a second conductive material on the first layer, the second conductive material being different from the first conductive material;

depositing a third layer of aluminum on the second layer;

anodizing the aluminum and creating a plurality of pores extending from the surface of the alumina towards the second layer;

removing a portion of the second conductive layer between the end of the pore and the first conductive layer.

40. The method of claim 39 wherein said removing is by etching.

41. The method of claim 40 wherein said etching is by bombardment of ions of inert gas.

42. The method of claim 39 which further comprises depositing a layer of catalytic material and growing a carbon nanotube in each pore from the catalytic material.

43. The method of claim 42 which further comprises establishing electrical communication between each nanotube and the third conductive layer.

44. The method of claim 43 wherein said establishing is be depositing a third conductive material in each pore after said growing.

45. The method of claim 44 wherein the third conductive material is palladium.

46. The method of claim 39 wherein the second conductive material is titanium.

47. The method of claim 39 wherein the insulating material includes silicon.

48. A method for growing nanotubes, comprising:

providing a substrate comprising an insulating material;

depositing a first layer of a first conductive material on the substrate;

depositing a second layer of a catalytic material on the first layer;

depositing a third layer of material on the second layer;

coating the third layer with a resist material;

exposing a pattern in the resist material;

etching the exposed pattern and creating a corresponding pattern of pits in the top surface of the third layer;

oxidizing the third material and creating a pore from each pit that extends generally normal to the top surface of the third material.

growing a nanotube within each pore from the catalytic material.

49. The method of claim 48 wherein the first conductive material is titanium.

50. The method of claim 48 wherein the catalytic material is one of Fe, Co, or Ni.

51. The method of claim 48 wherein the third layer of material is aluminum.

52. The method of claim 51 wherein said oxidizing is by anodizing the aluminum.

53. The method of claim 48 wherein said exposing a pattern is with electron beam lithography.

54. The method of claim 48 wherein said exposing a pattern is by photolithograph.

55. The method of claim 48 wherein said etching is a wet etch.

56. The method of claim 48 which further comprises removing the resist material before said anodizing.

57. The method of claim 48 wherein said growing is by chemical vapor deposition.

58. The method of claim 57 wherein the CVD is microwave-enhanced.

59. The method of claim 48 which further comprises applying a glass on the top surface of the third material and within each pore surrounding the respective nanotube.