CONTACTLESS TECHNIQUE FOR EVALUATING A FABRICATION OF A WAFER

• US 20100304509A1
• Filed: 06/01/2010
• Published: 12/02/2010
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Gary L. Steinbrueck, Jose J. Estabil, Majid Aghababazadeh, Nader Pakdaman
• Original Assignee: Gary L. Steinbrueck, Jose J. Estabil, Majid Aghababazadeh, Nader Pakdaman
• Inventors: Pakdaman, Nader, Aghababazadeh, Majid, Steinbrueck, Gary L., Estabil, Jose J.
• Granted Patent: US 8,990,759 B2
• Time in Patent Office: Days
• US Class Current: 438/17
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. A method for evaluating a fabrication of at least a portion of a wafer, the method comprising:

when the wafer is in a partially fabricated state, determining, at a plurality of locations on an active area of a die of the wafer, a value of a specified performance parameter, wherein the specified performance parameter is known to be indicative of a particular fabrication process in the fabrication; and

obtaining evaluation information based on a variance of the value of the performance parameter at the plurality of locations, wherein the step of obtaining evaluation information is performed without affecting a usability of a chip that is created from the die, and wherein the evaluation information is for evaluating how one or more processes that include the particular fabrication process in the fabrication of the wafer were performed.

2. The method of claim 1, wherein the step of obtaining evaluation information includes determining a variance of the value of the performance parameter at different locations in the plurality of locations.

3. The method of claim 1, wherein the step of obtaining evaluation information includes determining a spatial variance of the value of the performance parameter at the plurality of locations.

4. The method of claim 1, wherein the step of obtaining evaluation information includes determining a variance of switching characteristics from one or more structures disposed at the plurality of locations.

5. The method of claim 1, further comprising the step of correlating the specified performance parameter to one or more steps in the fabrication of the wafer.

6. The method of claim 1, further comprising the step of evaluating how one or more steps in the fabrication are performed using the evaluation information.

7. The method of claim 1, further comprising the step of correlating the specified performance parameter to an attribute of a device on the die;

wherein the attribute is a result of one or more steps in the fabrication of the wafer.

8. The method of claim 7, wherein the step of correlating the specified performance parameter to an attribute of a device on the die includes correlating the specified performance parameter to a gate length or gate width variation of any one or more switching elements on the die;

wherein the gate length or gate width variation is a result of one or more steps in the fabrication of the wafer.

9. The method of claim 7, wherein the step of correlating the specified performance parameter to an attribute of a device on the die includes correlating the specified performance parameter to a capacitance characteristic on any portion of the die;

wherein the capacitance characteristic is a result of one or more steps in the fabrication of the wafer.

10. The method of claim 7, wherein the step of correlating the specified performance parameter to an attribute of a device on the die includes correlating the specified performance parameter to a resistance characteristic on any portion of the die;

wherein the resistance characteristic results from the fabrication of the wafer.

11. The method of claim 7, wherein the step of correlating the specified performance parameter to an attribute of a device on the die includes correlating the specified performance parameter to an electrical bias characteristic on any portion of the die, wherein the electrical bias characteristic results from the fabrication of the wafer.

12. The method of claim 7, wherein the attribute is a result of one or more steps for etching the wafer including planarization.

13. The method of claim 11, wherein the attribute is a result of one or more steps for performing a lithography process performed on the wafer.

14. The method of claim 7, wherein the step of correlating the specified performance parameter to an attribute of a device on the die includes correlating the specified performance parameter to a resistivity variation of any one or more switching elements on the die;

wherein the resistivity variation is a result of one or more steps in the fabrication of the wafer.

15. The method of claim 2, wherein the step of obtaining evaluation information includes isolating one or more steps in the fabrication of the wafer as attributing to the variance of the value of the performance parameter.

16. The method of claim 1, wherein the step of obtaining evaluation information includes measuring, from a circuit element disposed at each of the plurality of locations on the die, at least one of (i) a switching speed, (ii) circuit delay and (iii) slew rate.

17. The method of claim 2, further comprising the step of adjusting how the one or more steps in the fabrication of the wafer are performed using the measured variance.

18. The method of claim 2, wherein the step of obtaining evaluating information includes obtaining information for correlating the variance to a specific fabrication step or sequence.

19. The method of claim 1, wherein obtaining evaluation information includes obtaining information on how one or more processes in the fabrication are performed from a set of processes consisting of:

a lithography process, an etch process, a deposition process, a polishing process, and an interconnectivity process.

20. The method of claim 1, wherein the step of obtaining evaluation information includes obtaining the evaluation information without contacting or electrically affecting a performance of the chip.