MULTI-MAPPED FLASH RAID

• US 20100306452A1
• Filed: 06/02/2009
• Published: 12/02/2010
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Weber, Bret S., Ober, Robert E., Hoglund, Timothy E.
• Granted Patent: US 9,323,658 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Disclosed is a storage system. The storage system includes a redundant array of inexpensive disks (RAID) controller. The RAID controller includes a flash memory controller coupled to a flash memory. The flash memory controller may perform background management tasks. These include logging and error reporting, address translation, cache table management, bad block management, defect management, wear leveling, and garbage collection. The array controller also allows the flash memory to be divided into multiple mappings.

Claims

1. A storage array controller, comprising:

a RAID controller;

a flash memory controller configured to map a first range of flash memory as an I/O device, and a second range of flash memory as system memory.

2. The storage array controller of claim 1, wherein said second range of flash memory is mapped in a PCIe address space.

3. The storage array controller of claim 1, wherein said flash memory controller manages address translations between said I/O device addresses and said first range of flash memory.

4. The storage array controller of claim 1, wherein said flash memory controller distributes flash memory writes to increase flash memory lifetime.

5. The storage array controller of claim 1, wherein said flash memory controller prevents data from being read from a defective flash memory block.

6. The storage array controller of claim 1, wherein said flash memory controller maps said first range of flash memory to a RAID logical unit.

7. The storage array controller of claim 1, wherein said flash memory controller uses said second range of flash memory as a disk data cache.

8. The storage array controller of claim 1, wherein said flash memory controller maps said first range of flash memory to a serial ATA logical unit.

9. A computer peripheral, comprising:

a RAID controller projecting a first disk drive as a first logical unit number; and

,

a flash controller, integrated with said RAID controller, projecting a first address range of a flash memory device as a second logical unit number.

10. The computer peripheral of claim 9, wherein said flash controller projects a second address range of said flash memory device as a PCIe address space memory.

11. The computer peripheral of claim 9, wherein said flash controller manages address translations for said first address range and said second address range.

12. The computer peripheral of claim 9, wherein said flash controller distributes flash memory writes to increase flash memory lifetime.

13. The computer peripheral of claim 9, wherein said flash controller prevents data from being read from a defective flash memory block.

14. The computer peripheral of claim 9, wherein said flash controller projects said first address range of said flash memory device as a RAID logical unit.

15. The computer peripheral of claim 9, wherein said flash controller uses said second address range of said flash memory as a disk data cache.

16. The computer peripheral of claim 9, wherein said flash controller projects said second address range of said flash memory as a serial ATA logical unit.