SYSTEM AND METHOD FOR INTEGRATED TIMING CONTROL FOR AN LCD DISPLAY PANEL

• US 20100309392A1
• Filed: 08/17/2010
• Published: 12/09/2010
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Zoran Corporation (Qualcomm, Inc.)
• Inventors: Chen, Chen, He, Lei
• Granted Patent: US 8,502,927 B2
• Time in Patent Office: Days
• US Class Current: 348/790
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A method of displaying an image. The method includes acts of receiving pixel data and pixel timing and control signals corresponding to the image, and formatting the pixel data based on a selected communication standard and a transmitter bit rate that corresponds to a number of pixel data bits to be transmitted each transmitter clock cycle. The method also includes an act of generating a clock signal based on the formatted pixel data, a bit rate of the selected communication standard, and the transmitter bit rate, the generated clock signal identifying a mapped bit rate at which the formatted pixel data is to be received by a television display during each cycle of the generated clock signal and which is different than the transmitter bit rate, and also includes the act of transmitting, at the transmitter bit rate, the formatted pixel data and the generated clock signal to the television display so that the formatted pixel data is received by the television display at the bit rate of the selected communication standard.

Claims

1. A method of displaying an image comprising acts of:

receiving pixel data and pixel timing and control signals corresponding to the image;

formatting the pixel data based on a selected communication standard and a transmitter bit rate that corresponds to a number of pixel data bits to be transmitted each transmitter clock cycle;

generating a clock signal based on the formatted pixel data, a bit rate of the selected communication standard, and the transmitter bit rate, the generated clock signal identifying a mapped bit rate at which the formatted pixel data is to be received by a television display during each cycle of the generated clock signal and which is different than the transmitter bit rate; and

transmitting, at the transmitter bit rate, the formatted pixel data and the generated clock signal to the television display so that the formatted pixel data is received by the television display at the bit rate of the selected communication standard.

2. The method of claim 1, further comprising an act of receiving, responsive to the generated clock signal, the formatted pixel data at the mapped bit rate.

3. The method of claim 1, wherein the act of generating the clock signal based on the formatted pixel data, the bit rate of the selected communication standard, and the transmitter bit rate includes acts of:

determining, for each bit of the formatted pixel data, a clock state in which the bit of formatted pixel data is to be transmitted to the television display;

responsive to the clock state being a low state, transmitting a first indicator corresponding to the bit of formatted pixel data; and

responsive to the clock state being a high state, transmitting a second indicator corresponding to the bit of formatted pixel data.

4. The method of claim 3, wherein the first indicator represents a logical low level and wherein the second indicator represents a logical high level.

5. The method of claim 1, wherein the selected communication standard is one of an RSDS communication standard and a mini-LVDS communication standard, and wherein the mapped bit rate is 2 bits per cycle of the generated clock signal.

6. The method of claim 5, wherein the transmitter bit rate is 8 bits per clock cycle.

7. The method of claim 5, wherein the transmitter bit rate is 4 bits per clock cycle.

8. The method of claim 1, wherein the act of formatting the pixel data based on the selected communication standard and the transmitter bit rate includes an act of consecutively transmitting a single bit of pixel data.

9. The method of claim 1, wherein the act of formatting the pixel data based on the selected communication standard and the transmitter bit rate comprises acts of:

storing bits of pixel bit data in a register; and

accessing the bits of the pixel data stored in the register.

10. The method of claim 1, further comprising acts of:

storing generated clock signal data in a register;

accessing the generated clock signal data stored in the register; and

transmitting the generated clock signal data at the transmitter clock rate.

11. The method of claim 1, wherein the transmitter bit rate is higher than the mapped bit rate.

12. A television display system comprising:

a data framer configured to receive pixel data and pixel timing and control signals corresponding to an image, format the pixel data based on a selected communication standard and a transmitter bit rate that corresponds to a number of pixel data bits to be transmitted each transmitter clock cycle, and generate a clock signal based on the formatted pixel data, a bit rate of the selected communication standard, and the transmitter bit rate, the generated clock signal identifying a mapped bit rate at which the formatted pixel data is to be received by a television display during each cycle of the generated clock signal and which is different than the transmitter bit rate; and

a transmitter configured to transmit, at the transmitter bit rate, the formatted pixel data and the generated clock signal to the television display so that the formatted pixel data is received by the television display at the bit rate of the selected communication standard.

13. The system of claim 12, further comprising an integrated timing controller configured to receive the pixel timing and control signals and transmit the pixel timing and control signals to a source driver and a gate driver of a television display panel.

14. The system of claim 12, wherein the transmitter comprises a plurality of channel drivers, and wherein the transmitter is configured to transmit, responsive to a selection of at least one channel driver of the plurality of channel drivers, the formatted clock signal data on the at least one channel driver of the plurality of channel drivers.

15. The system of claim 14, wherein the transmitter does not include a clock driver incorporating a phase-locked loop.

16. The system of claim 14, wherein the transmitter does not include a dedicated clock driver that is structurally different than each of the plurality of channel drivers.

17. The system of claim 12, further comprising a register configured to format and store bits of pixel data, wherein the transmitter is configured to access the bits of pixel data stored in the register and transmit the pixel bit data at the transmitter clock rate.