Compensation Of Phase Lock Loop (PLL) Phase Distribution Caused By Power Amplifier Ramping

• US 20100315140A1
• Filed: 06/12/2009
• Published: 12/16/2010
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Mayer, Thomas, Kissing, Jens, Kreienkamp, Rainer
• Granted Patent: US 8,058,917 B2
• Time in Patent Office: Days
• US Class Current: 327/159
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

Claims

1. A system comprising:

a power amplifier; and

a phase lock loop comprising;

an integrator module to generate a control signal, with the control signal altering an output signal of the phase lock loop such that the output signal is locked to a reference signal, the power amplifier receiving the output signal; and

a differentiator module selectively enabled such that the phase lock loop is switchable between a type I mode and a type II mode depending upon a power state of the power amplifier.

2. The system of claim 1 further comprising a digitally controlled oscillator (DCO) module to receive the control signal and generate the output signal;

3. The system of claim 2 further comprising a time-to-digital (TDC) converter module configured to determine a relative phase difference between the output signal and the reference signal to define a comparison signal.

4. The system of claim 3 further comprising a digital loop filter module configured to receive the comparison signal and generate a first signal based upon the comparison signal.

5. The system of claim 4 wherein the integrator module further accumulates the phase error in the first signal to generate the control signal.

6. The system of claim 5 wherein the differentiator module is coupled between the integrator module and the digital loop filter.

7. The phase lock loop of claim 1 wherein the power amplifier generates a feedback signal comprising a harmonic with the same frequency of the output signal.

8. The phase lock loop of claim 1 wherein the power amplifier amplifies the output signal.

9. The phase lock loop of claim 1 wherein the phase lock loop is switchable without generating additional disturbances within the phase lock loop.

10. A phase lock loop comprising:

a digitally controlled oscillator (DCO) module to receive a control signal and generate an output signal;

a power amplifier module to receive the output signal;

a time-to-digital (TDC) converter module configured to determine a relative phase difference between the output signal and a reference signal to define a comparison signal;

a digital loop filter module configured to receive the comparison signal and generate a first signal based upon the comparison signal;

an integrator module to accumulate the phase error in a second signal and generate the control signal, with the control signal altering the output signal such that the output signal is locked to the reference signal; and

a differentiator module coupled between the integrator module and the digital loop filter, the differentiator module comprising a flip-flop having an enable input and an adder/subtractor, wherein the flip-flop is selectively enabled such that;

i) when enabled, the adder/subtractor determines a difference between the first signal and a third signal that is output by the flip-flop and outputs this difference as the second signal, the phase lock loop being in a type I mode; and

ii) when not enabled, the adder/subtractor determines a difference between the first signal and a previous value of the third signal that is output by the flip-flop and outputs this difference as the second signal, the phase lock loop being in a type II mode.

11. The phase lock loop of claim 10 wherein the differentiator module is switchable between the type I mode and the type II mode depending upon a power state of the power amplifier.

12. The phase lock loop of claim 10 wherein the power amplifier generates a feedback signal comprising a harmonic with the same frequency of the output signal.

13. The phase lock loop of claim 10 wherein the power amplifier amplifies the output signal.

14. The phase lock loop of claim 10 wherein the phase lock loop is switchable without generating additional disturbances within the phase lock loop.

15. The phase lock loop of claim 10 wherein the flip flop is a D flip flop.

16. A wireless device comprising the phase lock loop of claim 10.

17. A method comprising:

determining a power state of a power amplifier to receive an output signal of a phase lock loop;

enabling the phase lock loop in type II mode when the power state of the power amplifier is constant; and

enabling the phase lock loop in type I mode when the power state of the power amplifier is ramping.

18. The method of claim 17 wherein enabling the phase lock loop in type II mode further comprises setting an enable signal of a differentiator module to zero such that a differentiator module is not enabled.

19. The method of claim 17 wherein enabling the phase lock loop in type I mode further comprises setting an enable signal of a differentiator module to logical high such that a differentiator module is enabled

20. The method as recited in claim 17 further comprising compensating for a feedback signal comprising a harmonic with the same frequency of an output signal of the phase lock loop, the feedback signal generated by the power amplifier.

21. The method as recited in claim 17 further comprising switching between the type I mode and the type II mode of the phase lock loop without generating additional disturbances within the phase lock loop.

22. A system comprising:

a power amplifier; and

a phase lock loop comprising;

a digital loop filter module to generate a control signal, with the control signal altering an output signal of the phase lock loop such that the output signal is locked to a reference signal, the power amplifier receiving the output signal; and

with a transfer function of the digital loop filter module being switchable between a low pass filter with integrating behavior (pole at s=0) and a low pass filter without integrating behavior to enable changing of a behavior of the phase lock loop depending upon a power state of the power amplifier.

23. A system comprising:

a transceiver module; and

a phase lock loop associated with the transceiver module, the phase lock loop to operate in a type I mode when the transceiver module is in a first state and to operate in a type II mode when the transceiver module is in a second state.

24. The system according to claim 23, further comprising a power amplifier associated with the transceiver module, the power amplifier determining the first and second states.

25. The system according to claim 24, wherein the first state is to occur when the power amplifier is ramping and the second state is to occur when the power amplifier is in a substantially constant state.