CONTROLLING ELECTROMECHANICAL BEHAVIOR OF STRUCTURES WITHIN A MICROELECTROMECHANICAL SYSTEMS DEVICE

• US 20100320555A1
• Filed: 08/23/2010
• Published: 12/23/2010
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Batey, John, Chui, Clarence, Miles, Mark W., Kothari, Manish, Tung, Ming-Hau
• Granted Patent: US 8,278,726 B2
• Time in Patent Office: Days
• US Class Current: 257/433
• CPC Class Codes: B81B 3/0086 Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
• CPC Class Codes: B81C 2201/0109 Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2201/053 Depositing a protective layers
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26

Abstract

In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device.

Claims

1. An electromechanical device having a substrate comprising:

an electrode layer formed over the substrate;

a dielectric layer formed over the electrode layer;

a first etch barrier layer formed over the dielectric layer;

a second etch barrier layer formed over the first etch barrier layer; and

a moving layer located above the second etch barrier.

2. The device of claim 1, additionally comprising a cavity located between the second etch barrier layer and the moving layer.

3. The device of claim 1, additionally comprising a sacrificial layer located between the second etch barrier layer and the moving layer.

4. The device of claim 3, wherein the second etch barrier layer comprises a material resistant to an etch used to pattern the sacrificial layer.

5. The device of claim 3, wherein the first etch barrier layer comprises a material resistant to an etch used to remove the sacrificial layer.

6. The device of claim 1, wherein the second etch barrier layer comprises a material substantially resistant to a phosphoric/acetic/nitric acid etch.

7. The device of claim 1, wherein the first etch barrier layer comprises a material substantially resistant to a XeF₂ etch.

8. The device of claim 1, wherein the second etch barrier layer comprises silicon oxide.

9. The device of claim 8, wherein the dielectric layer comprises silicon oxide and the first etch barrier layer comprises aluminum oxide.

10. The device of claim 8, wherein the dielectric layer comprises a charge trapping layer.

11. The device of claim 1, wherein the second etch barrier layer comprises silicon nitride.

12. The device of claim 11, wherein the first etch barrier layer comprises aluminum oxide, and wherein the dielectric layer comprises a material selected from the group of:

silicon oxide and silicon nitride.

13. The device of claim 1, wherein the second etch barrier layer comprises a material selected from the group of titanium, molybdenum, and amorphous silicon.

14. The device of claim 1, wherein the second etch barrier layer has a varying thickness over the surface of the first etch barrier layer.

15. The device of claim 14, wherein the second etch barrier covers only a portion of the first etch barrier layer.

16. A MEMS device, comprising:

means for conducting an electrical signal;

means for supporting said conducting means;

means for electrically insulating said conducting means;

first protecting means for protecting said insulating means;

second protecting means for protecting said first protecting means; and

means for defining a cavity having a variable size.

17. The device of claim 16 wherein:

the supporting means comprises a transparent substrate;

the conducting means comprises an electrode layer formed over the transparent substrate; and

the means for defining a cavity comprises a movable layer spaced apart from the second protecting means.

18. The device of claim 16, wherein the insulating means comprises a dielectric layer formed over the conducting means.

19. The device of claim 16, wherein the first protecting means comprises a first etch barrier layer formed over the insulating means.

20. The device of claim 16, wherein the second protecting means comprises a second etch barrier layer formed over said first protecting means.

21. A method of manufacturing a MEMS device, comprising:

depositing an electrode layer on a substrate;

depositing a dielectric layer over the electrode layer;

depositing an etch stop layer over the dielectric layer; and

depositing a protective layer over the etch stop layer.

22. The method of claim 21, wherein the etch stop layer comprises aluminum oxide, and wherein the dielectric layer comprises a material selected from the group of silicon nitride and silicon oxide.

23. The method of claim 21, wherein the etch stop layer comprises aluminum oxide, additionally comprising depositing a second layer of aluminum oxide over the electrode layer, wherein the dielectric layer is deposited over the second layer of aluminum oxide.

24. The method of claim 21, wherein the etch stop layer comprises aluminum oxide, the method additionally comprising:

depositing at least a first sacrificial layer over the protective layer;

depositing a reflective layer over the sacrificial layer; and

performing a release etch to remove the first sacrificial layer, thereby creating an interferometric cavity.

25. The method of claim 24, wherein performing the release etch comprises etching both the first sacrificial layer and the protective layer relative to the etch barrier layer.

26. The method of claim 24, wherein performing the release etch comprises etching the first sacrificial layer relative to the protective layer.

27. The method of claim 26, additionally comprising selectively etching the protective layer relative to the etch barrier layer, wherein etching the protective layer is done after performing the release etch.

28. The method of claim 24, additionally comprising:

performing a preliminary etch to remove a portion of the first sacrificial layer, thereby exposing a portion of the protective layer; and

depositing at least a second sacrificial layer over the first sacrificial layer;

wherein performing a release etch comprises removing the second sacrificial layer.

29. The method of claim 28, wherein the protective layer comprises a material selected from the group of:

silicon oxide, silicon nitride, amorphous silicon, molybdenum, and titanium.

30. The method of claim 28, wherein performing the preliminary etch removes at least a portion of the protective layer.

31. The method of claim 28, wherein performing the preliminary etch comprises selectively etching the first sacrificial layer relative to the protective layer.